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[VHDL-FPGA-Verilog] generic_fifo

Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
Platform: | Size: 20480 | Author: daiowen | Hits:

[OS Develop] FIFO

Description: 通用异步FIFO设计的verilog代码，来自于opencore-Universal Asynchronous FIFO Verilog design code, from opencore
Platform: | Size: 18432 | Author: zhangjing | Hits:

[VHDL-FPGA-Verilog] asynchronous-FIFO-structure

Description:
Platform: | Size: 545792 | Author: john | Hits:

[Windows Develop] sdh

Description: SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhead bytes, it contains a lot of important information, the procedures for receiving SDH overhead processing, search header, sub-frequency ,勤務if E1 asynchronous byte fifo. Removable for three source code, I do not know the three procedures can be arrived
Platform: | Size: 6144 | Author: 韩冰 | Hits:

[OS Develop] asyn_fifo

Description: verilog编写的异步fifo源代码，asyn_fifo.v为顶层，调用其他四个文件-asynchronous fifo prepared Verilog source code, asyn_fifo.v for top-level, call the other four documents
Platform: | Size: 2048 | Author: nihao | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 用verilog实现异步FIFO，代码中有两个模块，使用时注意顶层模块和底层模块，用quartus2即可打开直接使用。-Verilog using Asynchronous FIFO, the code has two modules, when the attention of top-level module and the bottom module, with direct access to open quartus2.
Platform: | Size: 2048 | Author: 杨帆 | Hits:

[Other] fifo

Description: a_fifo5.v verilog code for asynchronous FIFO-a_fifo5.v verilog code for asynchronous FIFO
Platform: | Size: 2048 | Author: Haris Kandath | Hits:

[VHDL-FPGA-Verilog] async_fifo

Description: verilog HDL写的异步fifo代码及测试平台，直接可用，可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for
Platform: | Size: 62464 | Author: 张晗 | Hits:

[VHDL-FPGA-Verilog] afifo

Description: verilog编写的异步FIFO代码，功能仿真时是正确的。-verilog code written in asynchronous FIFO, functional simulation is the right time.
Platform: | Size: 1024 | Author: 查乐 | Hits:

[VHDL-FPGA-Verilog] sdfsdFifo

Description: 这是一个异步fifo的Verilog 代码，该代码的功能是实现异步的first in first out-This is an asynchronous fifo in the Verilog code, the code' s function is to achieve asynchronous first in first out
Platform: | Size: 1024 | Author: Yongjie | Hits:

[VHDL-FPGA-Verilog] ad_da_ctr

Description: 基于FPGA的ad和da转换Verilog代码，FPGA采用ep2c5芯片，做成异步fifo，ad芯片采用TI的ths1230,da芯片采用TI的TLV5619，仿真结果基本正确。-FPGA-based ad and da conversion Verilog code, FPGA using ep2c5 chip, made ??of asynchronous fifo, ad-chip using TI s ths1230, da chip uses TI s TLV5619, simulation results are basically correct.
Platform: | Size: 2299904 | Author: ych | Hits:

[VHDL-FPGA-Verilog] AsynFIFO

Description: Verilog 代码 异步FIFO，可综合，综合效率高，cumming的经典方法。-Verilog code for asynchronous FIFO, Cumming s the classic method.
Platform: | Size: 32768 | Author: 郑宇龙 | Hits:

[VHDL-FPGA-Verilog] FIFO-verilog

Description: 两种异步FIFO设计以及源代码（Verilog）-Two asynchronous FIFO design and source code (Verilog)
Platform: | Size: 12288 | Author: 范先龙 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 异步FIFO Verilog源代码，对控制读写地址进行设计，以便写满和读空只产生一个标志，实现对FIFO的缓冲控制-Asynchronous FIFO Verilog source code, designed to control read and write addresses in order to fill and read empty produce only one flag, the FIFO buffer control
Platform: | Size: 3072 | Author: zx | Hits:

[VHDL-FPGA-Verilog] FIFOUART

Description: fpga实现的基于FIFO的异步串行通信代码，描述语言为Verilog-fpga-based FIFO asynchronous serial communication code description language Verilog
Platform: | Size: 2048 | Author: jiangliang | Hits:

[Windows Develop] aasyn_fiffos

Description: verilog编写的异步fifo源代码，asyn_fiifo.v为顶层，调用其他四个文件， -verilog prepared the the asynchronous fifo source code, asyn_fiifo.v for the top floor, calling the other four documents,
Platform: | Size: 2048 | Author: mmzz3211 | Hits:

[VHDL-FPGA-Verilog] FIFO-and-CAM

Description: verilog code for gray counter,synchronous and asynchronous fifo
Platform: | Size: 25600 | Author: Abhijeet | Hits:

[Other] fifo

Description: 异步fifo ,verilog 源代码，含工程文件，modosim 下运行-Asynchronous fifo verilog source code containing the project file run modosim
Platform: | Size: 175104 | Author: zhaoyibin | Hits:

[VHDL-FPGA-Verilog] async_fifo-and-verilog

Description: 异步fifo的详细原理分析说明及verilog源代码，经典推荐！-Detailed description of the principles and analysis of asynchronous fifo verilog source code, the classic recommendation!
Platform: | Size: 12288 | Author: 雨茗 | Hits:

[VHDL-FPGA-Verilog] 异步FIFO

Description: 自己编写的同步和异步FIFO的verilog代码，验证过，有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)
Platform: | Size: 2048 | Author: 大黄黄黄 | Hits:
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