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[VHDL-FPGA-Verilog] 数字锁相环

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
Platform: | Size: 124928 | Author: 于洪彪 | Hits:

[VHDL-FPGA-Verilog] 数字锁相环设计源程序

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF
Platform: | Size: 120832 | Author: 杰轩 | Hits:

[matlab] PLLSim

Description: 二阶锁相环Matlab仿真代码，如入两路信号和信噪比，输出锁相以后的信号。可以仿真初始频差，和频率斜升的情况-second-order PLL Matlab simulation code, such as two-way signals and signal to noise ratio, the output signal after the lock-in. Simulation can initial frequency difference, and frequency ramp-up of
Platform: | Size: 2048 | Author: 里根 | Hits:

[Post-TeleCom sofeware systems] DDScom

Description: 直接式数字锁相环频率合成器.用ELANIX公司SYSTEMVIEW运行.-direct digital PLL frequency synthesizer. SYSTEMVIEW ELANIX companies with operations.
Platform: | Size: 1024 | Author: a | Hits:

[Communication-Mobile] lmx2325-test

Description: PLL-LMX2325 C程序,用于锁相环频率控制-PLL-LMX2325 C procedures for the PLL frequency control
Platform: | Size: 1024 | Author: 千里沙鸥 | Hits:

[Communication-Mobile] pllset

Description: 三星的有关ARM9的S3C 系列的PLL频率设置软件，ARM开发中可以快速设置所需要的频率参数-Samsung's S3C the ARM9 series of PLL installed software, ARM development can quickly set up the required frequency parameters
Platform: | Size: 93184 | Author: 毛斌 | Hits:

[Program doc] PLL_PLV

Description: 锁相回路可视为一个输出相位和输入相位的回授系统用以同步输入参考讯号和回授后输出信号。并让其操作同样的频率。如(图一)所示，简单锁相回路[3,4]是由三个电路构成，分别为相位侦测器（Phase Detector）、回路滤波器（Loop Filter）、压控荡器（VCO）-phase-locked loop can be regarded as a phase output and input phase feedback system for synchronous reference input and feedback signals After the output signal. And allowed to operate the same frequency. If (Figure 1), the simple lock-loop [3,4] by the three circuit. for the detection phase (Phase Detector), loop filter (Loop Filter), VCO finishes (VCO)
Platform: | Size: 149504 | Author: 王浩 | Hits:

[Communication-Mobile] edm3jitrpll

Description: Jitter is extremely important in systems using PLL-based clock drivers. The effects of jitter range from not having any effect on system operation to rendering the system completely non-functional. This application note provides the reader with a clear understanding of jitter in high-speed systems. It introduces the reader to various kinds of jitter in high-speed systems, their causes and their effects, and methods of reducing jitter. This application note will concentrate on jitter in PLL-based frequency synthesizers.
Platform: | Size: 101376 | Author: 孙强 | Hits:

[VHDL-FPGA-Verilog] pll

Description: fpga中pll时钟实现的源代码，可实现倍频或分频-pll clock in the FPGA to achieve the source code, can be realized or sub-octave frequency
Platform: | Size: 3072 | Author: 张恒 | Hits:

[VHDL-FPGA-Verilog] PLL

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上； 顶层文件是PLL.GDF-Digital phase-locked loop PLL is the design source code, which, Fi is the input frequency (receive data), Fo (Q5) is a local output frequency. The purpose is to extract data from the input clock signal (Q5), their frequency and data rate in line clock rising edge of lock-in data on rising and falling edge PLL.GDF top-level document
Platform: | Size: 126976 | Author: 许伟 | Hits:

[Communication-Mobile] pll

Description: 一个实现任意倍频的，输入参考频率未知的pll，已综合实现-frequency multiple rely on dpll，unknown reference input clock
Platform: | Size: 4096 | Author: 刘彻 | Hits:

[matlab] pll

Description: A Matlab script to simulate a Phase-Locked Loop (PLL). This is a type II PLL ie it has two integrators (one of these is the VCO itself). It is simulated with an FM (frequency modulation) input. The output is the demodulated baseband signal
Platform: | Size: 1024 | Author: Tom_M | Hits:

[SCM] pll

Description: 频合锁相环LMX2326与单片机接口代码 -LMX2326 PLL frequency together with the single-chip interface code
Platform: | Size: 1024 | Author: haoluoye | Hits:

[VHDL-FPGA-Verilog] pll

Description: DPLL由 鉴相器、 模K加减计数器、脉冲加减电路、同步建立侦察电路、模N分频器构成. 整个系统的中心频率(即signal_in和signal_out的码速率的2倍)为clk/8/N. 模K加减计数器的K值决定DPLL的精度和同步建立时间,K越大,则同步建立时间长,同步精度高.反之则短,低. -DPLL by the phase detector, K addition and subtraction counter mode, pulse subtraction circuit, synchronous detection circuit established, constitute a model N divider. The whole system of the center frequency (ie signal_in and signal_out the code rate of 2 times) to clk/8/N. modulus K K value addition and subtraction counter DPLL decision to establish the accuracy and synchronization time, K is larger, the simultaneous establishment of a long time, synchronization accuracy. contrary is short and low.
Platform: | Size: 1024 | Author: 鬼舞十七 | Hits:

[Other] LM7001

Description: Direct PLL Frequency Synthesizers for Electronic Tuning
Platform: | Size: 79872 | Author: tanabe | Hits:

[VHDL-FPGA-Verilog] PLL

Description: 该测试程序用过Verilog HDL实现对PLL的分频，既频率管理功能-The Verilog HDL test procedure used to achieve the sub PLL frequency, only the frequency management function
Platform: | Size: 3072 | Author: Henin Lu | Hits:

[VHDL-FPGA-Verilog] pll(FPGA)

Description: 利用VHDL语言对FPGA进行锁相环倍频，经调试已经在开发板上实现倍频-The FPGA using VHDL language PLL frequency multiplier, the debug board has been achieved in the development of frequency
Platform: | Size: 361472 | Author: huangshaobo | Hits:

[SCM] ADF4351-V1.1(pll)

Description: PLL模块点频输出，可产生35Mhz~120Mhz稳定正弦信号(PLL point frequency output)
Platform: | Size: 370688 | Author: 健儿子 | Hits:

[SCM] dsPIC33 PLL settings

Description: 这是Microsoft Office 的Exel样式的计算软件。用这软件来很容易算出dsPIC33F单片机的PLL频率。(This is calculating program for frequency setting of dsPIC33F PLL.)
Platform: | Size: 87040 | Author: cnd4791 | Hits:

[matlab] pll

Description: 一个简短的锁相环程序，主要是和频率与相位阶跃有关的，里面有详细注释(A short phase-locked loop program, which is mainly related to frequency and phase step, with detailed comments)
Platform: | Size: 10240 | Author: 毛毛12345 | Hits:
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