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[Embeded-SCM Develop] EPM7064

Description: 刚刚学习CPLD的绝对有用，这是由altera公司MAX7000s系列组成的最小系统，CPLD为EPM7064，封装PLCC，绝对完整，包括原理图和PCB图，板子已经调试成功，注意用protel DXP打开，特别适合于CPLD初学者。-just learning CPLD absolutely useful, This is the company MAX7000s altera series consisting of the smallest system, CPLD for the EPM7064, Packaging, PLCC, absolute integrity, including schematic and PCB map Debugging plank has been successful, Protel DXP attention to the use of open, and are particularly suited to beginners CPLD.
Platform: | Size: 83912 | Author: yulei | Hits:

[Other resource] CPLDxiaoche

Description: 智能机器小车主要完成寻迹功能，由机械结构和控制单元两个部分组成。机械结构是一个由底盘、前后辅助轮、控制板支架、传感器支架、左右驱动轮、步进电机等组成。控制单元部分主要由主要包含传感器及其调理电路、步进电机及驱动电路、控制器三个部分。本设计的核心为控制器部分，采用Altera MAX7000S系列的EPM7064LC84-15作主控芯片。CPLD芯片的设计主要在MAX+plusⅡ10.0环境下利用VHDL语言编程实现。驱动步进电机电路主要利用ULN2803作为驱动芯片。 -intelligent machines trolley track of the major functions by mechanical structure and control modules of two components. Mechanical structure is a chassis, after supporting wheels, the control panel stent, sensors stent, driving wheel around, Stepper motors, and other components. Some of the main control unit from the mainly contains sensors and conditioning circuits, and stepper motor drive circuit, the controller of three parts. The design for the core controller, Altera MAX7000S the EPM7064LC84-15 for the control chip. CPLD chip design mainly in MAX II plus 10.0 environment using VHDL programming. Stepper motor driver circuit using mainly driven ULN2803 chip.
Platform: | Size: 1369 | Author: lili | Hits:

[Embeded-SCM Develop] EPM7064

Description: 刚刚学习CPLD的绝对有用，这是由altera公司MAX7000s系列组成的最小系统，CPLD为EPM7064，封装PLCC，绝对完整，包括原理图和PCB图，板子已经调试成功，注意用protel DXP打开，特别适合于CPLD初学者。-just learning CPLD absolutely useful, This is the company MAX7000s altera series consisting of the smallest system, CPLD for the EPM7064, Packaging, PLCC, absolute integrity, including schematic and PCB map Debugging plank has been successful, Protel DXP attention to the use of open, and are particularly suited to beginners CPLD.
Platform: | Size: 83968 | Author: yulei | Hits:

[VHDL-FPGA-Verilog] CPLDxiaoche

Description: 智能机器小车主要完成寻迹功能，由机械结构和控制单元两个部分组成。机械结构是一个由底盘、前后辅助轮、控制板支架、传感器支架、左右驱动轮、步进电机等组成。控制单元部分主要由主要包含传感器及其调理电路、步进电机及驱动电路、控制器三个部分。本设计的核心为控制器部分，采用Altera MAX7000S系列的EPM7064LC84-15作主控芯片。CPLD芯片的设计主要在MAX+plusⅡ10.0环境下利用VHDL语言编程实现。驱动步进电机电路主要利用ULN2803作为驱动芯片。 -intelligent machines trolley track of the major functions by mechanical structure and control modules of two components. Mechanical structure is a chassis, after supporting wheels, the control panel stent, sensors stent, driving wheel around, Stepper motors, and other components. Some of the main control unit from the mainly contains sensors and conditioning circuits, and stepper motor drive circuit, the controller of three parts. The design for the core controller, Altera MAX7000S the EPM7064LC84-15 for the control chip. CPLD chip design mainly in MAX II plus 10.0 environment using VHDL programming. Stepper motor driver circuit using mainly driven ULN2803 chip.
Platform: | Size: 1024 | Author: lili | Hits:

[SCM] faguanerjiguan

Description: 8个发光二级管，具有俩状态。状态一：单灯闪烁，一个灯闪烁，从左往右依次亮。 状态二：中间两灯先亮，然后向两边亮，直至全亮；然后从两边向中间熄灭。有仿真，可下载到MAX7000s EMP7128SLC84-15开发板。-Eight light-emitting diode with the two state. The state of a: single lights flashing, a flashing light, light from left to right order. State II: the middle of the two bright lights first, and then to the sides of light until the full light and then out toward the middle from both sides. There are simulation, can be downloaded to MAX7000s EMP7128SLC84-15 development board.
Platform: | Size: 125952 | Author: deng | Hits:

[VHDL-FPGA-Verilog] qiangdaqi

Description: 多路抢答器 VHDL语言设计 抢答器是各类竞赛常用的仪器设备之一，它能快速、准确地判决并显示出第一抢答者。本文作者采用MAXPLUSII 软件和MAX7000S芯片，提出了一种四路抢答器的设计方案。该方案具有判断准确、硬件电路简单、容易实现等优点。 关键字：抢答器 竞争 RS触发器 EDA -Multiple Responder Responder VHDL language design competition of various kinds of equipment used, it can quickly and accurately answer in the first sentence and show those. The author uses MAXPLUSII MAX7000S chip software and proposes a four-way Responder design. The program has to determine accurately, the hardware circuit is simple, easy to implement and so on. Keywords: Responder competitive EDA RS flip-flop
Platform: | Size: 80896 | Author: 王天宇 | Hits:

[VHDL-FPGA-Verilog] Lab2_Part1

Description: display BCD code(0-9) using 7-segment displays in verilog code. Implements on educational kit Altera MAX7000s EPM7128SLC84-7.
Platform: | Size: 25600 | Author: Henna Tan | Hits:

[VHDL-FPGA-Verilog] Lab2_Part2

Description: converts a 4-bit binary code to 2-digital BCD code in verilog code. Implements on educational kit Altera MAX7000s EPM7128SLC84-7.
Platform: | Size: 112640 | Author: Henna Tan | Hits:

[VHDL-FPGA-Verilog] part1

Description: a 4-bit synchronous counter using T-Flip Flops and AND gates in verilog code. Implements on educational kit Altera MAX7000s EPM7128SLC84-7.
Platform: | Size: 140288 | Author: Henna Tan | Hits:

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