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[VHDL-FPGA-Verilog] 数字锁相环

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
Platform: | Size: 124928 | Author: 于洪彪 | Hits:

[VHDL-FPGA-Verilog] 数字锁相环设计源程序

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF
Platform: | Size: 120832 | Author: 杰轩 | Hits:

[Other] easy_pll

Description: 锁相环设计文档和一个可执行文件-PLL design documents and an executable file
Platform: | Size: 108544 | Author: KC_P | Hits:

[Communication-Mobile] plltips

Description: 技术文章《采用PLL设计时需注意的问题》在工程设计中有参考价值-technical article, "using PLL design attention to the problem" in engineering design reference value
Platform: | Size: 435200 | Author: 李湘鲁 | Hits:

[Software Engineering] ADS-RF-FILTER-DESIGN

Description: ads 2005a 用来设计射频滤波器的材料！ 从计算到仿真，每一个步骤都很清楚！ 可作为相关开发人员的参考！ -ads 2005a used to design RF filter material! From the calculation of the simulation, each one steps are very clear. Related development as a reference!
Platform: | Size: 242688 | Author: xulingfei | Hits:

[Communication-Mobile] PLLDesignAssistant

Description: PLL design assistnat-- tells you how to design a good P
Platform: | Size: 7548928 | Author: marcus | Hits:

[Communication-Mobile] wb_digital_synthesizer.tar

Description: MIT的一个数字频综源代码，包括cadence的，CPPSIM（MIT做的PLL的设计软件）-MIT, a digital frequency synthesizer source code, including the cadence of, CPPSIM (MIT make the PLL design software)
Platform: | Size: 27648 | Author: hqh | Hits:

[matlab] pll-linear

Description: 该程序描述了二阶锁相环的环路滤波器的设计和线性模型分析-The program describes the second-order PLL loop filter design and linear model analysis
Platform: | Size: 1024 | Author: vie | Hits:

[VHDL-FPGA-Verilog] PLL

Description: PLL 时钟模块　　Quartus II平台的简单设计实例　附仿真波形-PLL clock module Quartus II platform attached to a simple design example simulation waveforms
Platform: | Size: 806912 | Author: 许东滨 | Hits:

[Software Engineering] PLL

Description: 国外一篇很好的数字锁相环（PLL）设计文档（解压后PLL.pdf），不可不看呦！-Abroad, a good digital phase-locked loop (PLL) design documents (after extracting PLL.pdf), can not look at Yo!
Platform: | Size: 352256 | Author: | Hits:

[Communication-Mobile] MHPerrottPhDThesis

Description: Ph.D thesis from M.H.Perrott, about Fractional-N PLL design.
Platform: | Size: 4283392 | Author: ge binjie | Hits:

[Books] Enablingtechniquesforlowpowerhighperformancefracti

Description: PhD.thesis about fractional PLL design from UC san-deago.
Platform: | Size: 778240 | Author: ge binjie | Hits:

[VHDL-FPGA-Verilog] pll

Description: 收集的数字锁相环设计相关文章多篇.主要采用VHDL语言进行设计.-Collection of digital phase-locked loop design articles related articles. Mainly VHDL design languages.
Platform: | Size: 10079232 | Author: gk | Hits:

[VHDL-FPGA-Verilog] PLL

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上； 顶层文件是PLL.GDF-Digital phase-locked loop PLL is the design source code, which, Fi is the input frequency (receive data), Fo (Q5) is a local output frequency. The purpose is to extract data from the input clock signal (Q5), their frequency and data rate in line clock rising edge of lock-in data on rising and falling edge PLL.GDF top-level document
Platform: | Size: 126976 | Author: 许伟 | Hits:

[OpenGL program] ysflight

Description: PLL design description in detail
Platform: | Size: 7172096 | Author: rais | Hits:

[matlab] pll

Description: 设计的软件锁相环的例子，自己写的，根据原理编的-PLL design example of software that he wrote, according to the principle for the
Platform: | Size: 2048 | Author: zhouxiaoshu | Hits:

[Windows Develop] PLL

Description: Programs for the book of Phase Locked Loop :design simulation and applications-Programs for the design of Phase Locked Loop circuits
Platform: | Size: 1704960 | Author: Kwan LO | Hits:

[Windows Develop] PLL(lin)

Description: 锁相环的设计主要用于载波跟踪代码，在载波跟踪捕获当中可能会用到的源代码-PLL design is mainly used for carrier tracking code, the carrier capture which may be used to track the source code
Platform: | Size: 1024 | Author: 小孙 | Hits:

[Crack Hack] pll

Description: Digital PLL design, all technic how to develope eficiency digital locked loop. All descriptions in English in details and examples
Platform: | Size: 112640 | Author: bugsmenow | Hits:

[matlab] Matlab-based-simulation-PLL-design-

Description: 基于Matlab仿真的数字锁相环的设计进行了详细的分析和模拟，数字和模拟锁相环的论文-Matlab-based simulation of digital PLL design, a thesis on digital and analog phase-locked loop for a detailed analysis and simulation
Platform: | Size: 2048 | Author: xufeng | Hits:
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