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[Other resource] rs-5-3

Description: 学习使用FPGA做一些简单的编码器,RS(5,3)编码就是5个字符中有5-3=2两个校正字
Platform: | Size: 992497 | Author: rubyshirial | Hits:

[Software Engineering] FPGAEPP.files

Description: USB、串口、并口是PC机和外设进行通讯的常用接口，但对于数据量大的图像来说，若利用串行RS-232协议进行数据采集，速度不能达到图像数据采集所需的要求；而用USB进行数据采集，虽能满足所需速度，但要求外设必须支持USB协议，而USB协议与常用工程软件的接口还不普及，给使用带来困难。有些用户为了利用标准并行口(SPP)进行数据采集，但SPP协议的150kb/s传输率对于图像数据采集，同样显得太低。因此,为了采集数据量大的图像数据,本文采用了具有较高传输速率的增强型并行口协议(EPP)和FPGA，实现对OV7620CMOS图像传感器进行高速数据采集，它最高速率可以达到2Mb/s。-USB, serial port, parallel port is PC and peripherals used for the communication interface, But for the large volume of data images, if the use of Serial RS-232 data acquisition agreement, speed image data can not achieve the requirements for acquisition; using USB for data collection, can meet the required speed, But requirements must support USB peripherals agreement, and USB agreement with the commonly used engineering software interface is not universal, difficult to use. Some users to take advantage of standard parallel port (SPP), for data collection, But SPP agreement of 150 kb/s transfer rate for image data acquisition, the same is too low. Therefore, in order to collect large quantities of data image data, In this paper, the high transmission rate of enhanced parallel port proto
Platform: | Size: 81920 | Author: yaoming | Hits:

[VHDL-FPGA-Verilog] vhdl_rs232

Description: 使用FPGA透过RS232与PC的作沟通，
Platform: | Size: 3072 | Author: 苏山河 | Hits:

[Com Port] RS232

Description: FPGA实现RS-232串口收发的Verilog程序，已经调通。-FPGA realization of RS-232 serial port to send and receive the Verilog procedures, Qualcomm has been transferred.
Platform: | Size: 2048 | Author: | Hits:

[Program doc] RS_decoder

Description: 高速RS编码算法及FPGA实现,一篇文章,写的很好,介绍了接收机中常用的RS编码的原理,指标与实现,觉得有用就看看吧.-High-speed RS coding algorithm and FPGA realization of an article written by a very good introduction of the RS receiver commonly used in coding theory, and implementation of indicators, find it useful to look at it.
Platform: | Size: 361472 | Author: zxx | Hits:

[VHDL-FPGA-Verilog] rs-5-3

Description: 学习使用FPGA做一些简单的编码器,RS(5,3)编码就是5个字符中有5-3=2两个校正字-Learning to use the FPGA to do a few simple encoders, RS (5,3) code is five characters in 5-3 = 2 has two correction words
Platform: | Size: 992256 | Author: rubyshirial | Hits:

[Communication-Mobile] 1

Description: RS译码的Euclid算法及其FPGA实现-RS decoding algorithm and its FPGA realization of Euclid
Platform: | Size: 54272 | Author: luvicee | Hits:

[Compress-Decompress algrithms] rs_encoder

Description: 一个很不错RS编码，用于DVB的信道编码，用VHDL语言编写，在FPGA上通过验证。-A very good RS encoder for DVB Channel Coding using VHDL language, in the FPGA-validated.
Platform: | Size: 3072 | Author: 杨宇 | Hits:

[VHDL-FPGA-Verilog] RSdecoder

Description: cpld/fpga RS(204,188)译码器的verilog程序-cpld/fpga RS (204,188) decoder of the Verilog program
Platform: | Size: 13312 | Author: 陈臣 | Hits:

[Communication-Mobile] rs

Description: rs编解码，对实现了rs码的编解码，并对其误码率进行了分析仿真-rs codec, to the achievement of the rs code coding and decoding, and BER analysis simulation
Platform: | Size: 1024 | Author: qibo | Hits:

[VHDL-FPGA-Verilog] uarts

Description: RS-232 interface example for FPGA/EDA developers
Platform: | Size: 2048 | Author: jools | Hits:

[VHDL-FPGA-Verilog] rs-codec(255-223)

Description: RS编码是一种纠错码，本程序实现RS（255，223）用FPGA 实现RS编码，程序在Quartus II中调试通过。-RS coding is an error-correcting codes, the procedures for the realization of RS (255,223) with FPGA realization of RS codes, in the Quartus II program through the debugger.
Platform: | Size: 20480 | Author: yux | Hits:

[VHDL-FPGA-Verilog] rs_5_3_gf256_latest.tar

Description: this paper deal with rs decoder algorithm-this paper deal with rs decoder algorithm
Platform: | Size: 781312 | Author: Ibrahim | Hits:

[Program doc] RS-decode_base-on-FPGA

Description: 这是一篇很精彩的硕士论文，里面详细论述了RS编译码的原理和实现方法，值得下载-This is a wonderful master rs decode thesis, which discusses in detail the RS encoding and decoding of the principle and method, it is worth to download! ! !
Platform: | Size: 3389440 | Author: 刘伟 | Hits:

[VHDL-FPGA-Verilog] RS-code

Description: 我测试过的！Verilog HDL实现RS编码。-I' ve tested it! RS coding Verilog HDL implementation.
Platform: | Size: 983040 | Author: kiekie | Hits:

[Program doc] RS3123

Description: Reed- So lomon (RS) 码是一种重要的纠错码, 它对随机性和突发性错误有极强的纠错能力, 广泛应用于 数字视频广播(DVB) 系统和其它数字通信领域。给出了一种GF (25) 域上的RS (31, 23) 编码器的实现算法, 介绍 了用现场可编程门阵列(FPGA ) 实现RS 编码器的原理和过程, 并给出了实现电路及其仿真的输出波形。-Reed-So lomon (RS) code is an important error-correcting code, its random and unexpected error has a strong error correction capabilities, widely used in digital video broadcasting (DVB) systems and other digital communications. Gives a GF (25) Domains RS (31, 23) algorithm of the encoder is introduced with a Field Programmable Gate Array (FPGA) RS encoder to achieve the principles and processes, and providing a circuit and simulation of the output waveform.
Platform: | Size: 360448 | Author: 王彬 | Hits:

[VHDL-FPGA-Verilog] RS

Description: 基于FPGA的RS编码，包括RS码的编码原理，RS电路的设计与实现-FPGA-based RS code, including the RS, the coding principle, RS Circuit Design and Implementation
Platform: | Size: 1132544 | Author: 陈凯 | Hits:

[VHDL-FPGA-Verilog] rs-232vhdl

Description: it is the code for doing interfacing between computer and fpga board through rs-232.
Platform: | Size: 1024 | Author: sundaram | Hits:

[VHDL-FPGA-Verilog] fec

Description: RS编码电路 ，包括乘法器的模块和编码部分 RS编码器\mula_0.v RS编码器\mula_1.v RS编码器\rscode.v(The RS encoding circuit includes a multiplier module and an encoding section RS encoder \mula_0.v RS encoder, \mula_1.v, RS encoder, \rscode.v)
Platform: | Size: 1024 | Author: ZJWANG | Hits:

[Documents] 基于FPGA的串口通信系统

Description: 该设计是基于 FPGA 的串口通信系统模拟仿真，通过对 RS-232 串行总线 接口的设计，掌握发送与接收电路的基本思路，并进行串口通信。采用 Verilog HDL 语言对 UART 波特率产生模块、数据发送模块、接收模块进行硬件描述， 再将其整合为一个 RS-232 收发模块，最终在顶层模块中将两个 RS-232 模块例 化，实现两块 FPGA 芯片全双工通信的设计。(Design of serial communication system based on FPGA)
Platform: | Size: 578560 | Author: 小可大本 | Hits:
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