Search - RS vhdl code

[Applications] RS encoder(Verilog)

Description: RS编码的源代码使用Verilog在Xinloinx平台-RS coding using the source code in Verilog Xinloinx platform
Platform: | Size: 5120 | Author: 王锋 | Hits:

[VHDL-FPGA-Verilog] gongcehngsheji_477-2

Description: 使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真-use of the VHDL simulation software in achieving RSC (recursive convolution system) code encoding and decoding hardware simulation
Platform: | Size: 6144 | Author: 李超 | Hits:

[VHDL-FPGA-Verilog] RS232-for-vdhl

Description: RS232通讯VHDL源代码,MAXPLUS 2环境执行通过-RS232 communications VHDL source code, Segments 2 environment through implementation
Platform: | Size: 161792 | Author: lq | Hits:

[Post-TeleCom sofeware systems] rs-code

Description: 基于PLD的RS码编译码器设计，用VHDL语言编写，编译通过，测试结果正确。-PLD-based encoding and decoding of RS code design, using VHDL language, the compiler is passed, the test results correctly.
Platform: | Size: 15360 | Author: li.j | Hits:

[VHDL-FPGA-Verilog] rs-5-3

Description: 学习使用FPGA做一些简单的编码器,RS(5,3)编码就是5个字符中有5-3=2两个校正字-Learning to use the FPGA to do a few simple encoders, RS (5,3) code is five characters in 5-3 = 2 has two correction words
Platform: | Size: 992256 | Author: rubyshirial | Hits:

[VHDL-FPGA-Verilog] RS232

Description: quatus II 环境下vhdl实现RS232功能-quatus II environment realize RS232 VHDL functional
Platform: | Size: 437248 | Author: 王艳华 | Hits:

[source in ebook] RSencode

Description: 包含RS（10，8）的verilog源程序，加法器的verilog源程序，卷积码的verilog源程序-Contains RS (10,8) of the Verilog source code, the Verilog source code adder, convolution of the Verilog source code
Platform: | Size: 1024 | Author: bai | Hits:

[Windows Develop] MC-ACT-RSENC_DS

Description: MemecCoreReed-Solomon coding is a method of forward error correction in the form of block coding. Block coding consists of calculating a number of parity symbols over a number of message symbols. The parity symbols are appended to the end of the message symbols forming a codeword. Reed-Solomon coding is described in the form RS(n,k), where k is the number of message symbols in each block and n is the total number of symbols in the codeword. The value t defines the number of symbols that can be corrected by the Reed-Solomon code, where t=(n-k)/2 and the number of parity symbols is equal to 2t.
Platform: | Size: 95232 | Author: 张波 | Hits:

[VHDL-FPGA-Verilog] uart_transmitter

Description: Very good info. for RS-232 transmitter VHDL code .
Platform: | Size: 1024 | Author: wan mi | Hits:

[VHDL-FPGA-Verilog] uart_receiver

Description: Very good info. for RS-232 receive VHDL code .
Platform: | Size: 1024 | Author: wan mi | Hits:

[Communication-Mobile] RSencoder

Description: 关于rs码编码器的相关程序，利用硬件语言实现-Rs encoder code on the relevant procedures, take advantage of the hardware language
Platform: | Size: 5120 | Author: 庄镒鹏 | Hits:

[VHDL-FPGA-Verilog] rs-codec-8-16

Description: RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
Platform: | Size: 27648 | Author: 饶进平 | Hits:

[Streaming Mpeg4] rs_encode

Description: 这是用verilog编写的RS（204，188）代码，适用于数字电视的BCH编码过程。-This is the verilog prepared using RS (204,188) code, the application of digital television in the course of the BCH code.
Platform: | Size: 2048 | Author: 蕊宫獍雪 | Hits:

[VHDL-FPGA-Verilog] RS

Description: reed selemon encoder vhdl code
Platform: | Size: 77824 | Author: mohamed saad | Hits:

[VHDL-FPGA-Verilog] RS-code

Description: 我测试过的！Verilog HDL实现RS编码。-I' ve tested it! RS coding Verilog HDL implementation.
Platform: | Size: 983040 | Author: kiekie | Hits:

[VHDL-FPGA-Verilog] RS-5-3-CODE

Description: RS(5,3）编码器原程序程序已经调试过且比较简短-RS(5,3） coder ,this code is very short
Platform: | Size: 465920 | Author: ai锋聆 | Hits:

[VHDL-FPGA-Verilog] RS

Description: RS编码器的VHDL源程序,程序有点大，不过能用。-RS encoder VHDL source code, program a little big, but can be used.
Platform: | Size: 897024 | Author: lcz | Hits:

[VHDL-FPGA-Verilog] RS

Description: 基于FPGA的RS编码，包括RS码的编码原理，RS电路的设计与实现-FPGA-based RS code, including the RS, the coding principle, RS Circuit Design and Implementation
Platform: | Size: 1132544 | Author: 陈凯 | Hits:

[VHDL-FPGA-Verilog] RS

Description: RS译码器的设计，使用RS码设计的译码器-RS decoder design, the use of RS code decoder design
Platform: | Size: 12288 | Author: 许皓天 | Hits:

[ELanguage] rs(31-19)

Description: 本源代码是RS（31,19）编码器的顶端实现程序和测试程序，此程序可以验证编码器工作与否。此代码，已在ModelSim验证通过。并附上测试时所产生的结果图像。-Source code is RS (31,19) encoder to achieve the top programs and testing procedures, this program can verify the encoder to work or not. This code has been verified in ModelSim. Together with the result when the test images.
Platform: | Size: 376832 | Author: jianghong | Hits:

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[Applications] RS encoder(Verilog)

[VHDL-FPGA-Verilog] gongcehngsheji_477-2

[VHDL-FPGA-Verilog] RS232-for-vdhl

[Post-TeleCom sofeware systems] rs-code

[VHDL-FPGA-Verilog] rs-5-3

[VHDL-FPGA-Verilog] RS232

[source in ebook] RSencode

[Windows Develop] MC-ACT-RSENC_DS

[VHDL-FPGA-Verilog] uart_transmitter

[VHDL-FPGA-Verilog] uart_receiver

[Communication-Mobile] RSencoder

[VHDL-FPGA-Verilog] rs-codec-8-16

[Streaming Mpeg4] rs_encode

[VHDL-FPGA-Verilog] RS

[VHDL-FPGA-Verilog] RS-code

[VHDL-FPGA-Verilog] RS-5-3-CODE

[VHDL-FPGA-Verilog] RS

[VHDL-FPGA-Verilog] RS

[VHDL-FPGA-Verilog] RS

[ELanguage] rs(31-19)

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