Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - VERILOG Stopwatch

Search list

[Embeded-SCM Develop] paobiao

Description: 用verilog写的跑表程序--Stopwatch program written by verilog.
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] eclock

Description: MAXPULS II 下VHDL实现多功能电子钟的源代码，包括时钟，秒表，日历等多种功能-MAXPULS II under VHDL multifunctional electronic clock source code, including the clock, stopwatch, multiple functions such as calendar
Platform: | Size: 3072 | Author: 余远恒 | Hits:

[Other] PAOBIAO_V

Description: 带音乐功能的跑表VerilogHDL描述-music with the stopwatch Verilog HDL description
Platform: | Size: 4096 | Author: nil | Hits:

[VHDL-FPGA-Verilog] shuzimiaobiao

Description: 用verilog实现了一个数字秒表的设计-verilog achieved using a digital stopwatch Design
Platform: | Size: 1024 | Author: qihuolin | Hits:

[Home Personal application] digtalclk

Description: 用Altera公司的QuartusII编写的电子钟程序，可以下载至开发板，实现一个智能数字钟功能，计时，校时，闹钟，跑表等功能，也可用于学习verilog HDL语言与数字逻辑-Using Altera s QuartusII procedures for the preparation of electronic bell, you can download to a development board, the realization of an intelligent digital clock function, time, school time, alarm clock, stopwatch functions can also be used to study verilog HDL language and digital logic
Platform: | Size: 2094080 | Author: 张欢 | Hits:

[VHDL-FPGA-Verilog] watch

Description: 用FPGA实现带马表日历的电子表，verilog代码。-Using FPGA to achieve with digital watches stopwatch calendar, verilog code.
Platform: | Size: 3072 | Author: nothing | Hits:

[VHDL-FPGA-Verilog] stop_watch

Description: 采用Quartus2编写的电子秒表电路 实现计时、暂停等功能-Quartus2 prepared using electronic stopwatch timer circuit, suspension and other functions
Platform: | Size: 349184 | Author: gz208 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: VERILOG设计实例，非常详细的例子，有交通灯，频率计，数字跑表等等例子-Verilog design example, a very detailed examples have traffic lights, frequency meter, digital stopwatch, etc. Examples of
Platform: | Size: 159744 | Author: luojinwen | Hits:

[VHDL-FPGA-Verilog] secondwatch

Description: 用VERILOG实现的秒表 用VERILOG实现的秒表-Realized by Verilog Verilog achieved using a stopwatch stopwatch
Platform: | Size: 393216 | Author: wwyjs163 | Hits:

[VHDL-FPGA-Verilog] wtut_ver

Description: verilog HDL语言编写的数字秒表，仿真已经通过，可供参考-verilog HDL language digital stopwatch, simulation has already been adopted, for reference
Platform: | Size: 26624 | Author: 邢继元 | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: Quartus II工程压缩文件，是一个典型的基于FPGA的秒表工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based project of the stopwatch, a 50MHz frequency, counting, decoding modules. Using VHDL language.
Platform: | Size: 464896 | Author: kg21kg | Hits:

[.net] StopWatch

Description: 用C#写的跑表，用于学习Timer控件和C#下的stopwatch类，在VS.net 2005下运行通过.-Using C# to write the stopwatch for the study and Timer controls and C# under the stopwatch class, VS.net 2005 in the run through.
Platform: | Size: 38912 | Author: weixin | Hits:

[VHDL-FPGA-Verilog] StopWatch

Description: Verilog 编写的 秒表程序，在数码管上显示，带有清0和暂停键-Stopwatch Implemented by Verilog hdl
Platform: | Size: 584704 | Author: 洪磊 | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: The program is written in verilog to accomplish functions of a stopwatch. It can be implemented in Xilinx FPGA spartan 3 board.
Platform: | Size: 2048 | Author: flyingwings | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: verilog 秒表程序 用quartus 编写-Verilog stopwatch ............................................................................................
Platform: | Size: 431104 | Author: icer | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: 这个程序是用verilog语言编写的秒表的小程序，可以精确到秒，有具体的程序，在开发板上实验成功！-This program is written in verilog stopwatch with a small program that can accurately to the second, there are specific procedures, the development board experiment is successful!
Platform: | Size: 1391616 | Author: 欢欢 | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: 用Verilog编写的秒表，可以实现计时、复位、暂停等功能。-stopwatch using Verilog language
Platform: | Size: 486400 | Author: 陈璜骁 | Hits:

[VHDL-FPGA-Verilog] Verilog秒表设计

Description: 用verilog在basys2开发板上实现一个具有置零、开始、暂停、记忆功能的秒表。(Implement a stopwatch which containing reset,pause,start,memory functions with the verilog on the vivado based on the basys2 development board.)
Platform: | Size: 637952 | Author: terriao | Hits:

[VHDL-FPGA-Verilog] verilog-stopwatch-master

Description: verilog stop watch code for end user
Platform: | Size: 10240 | Author: nira | Hits:

[VHDL-FPGA-Verilog] StopWatch

Description: 利用Verilog实现数字秒表（基本逻辑设计分频器练习） 设置复位开关。当按下复位开关时，秒表清零并做好计时准备。在任何情况下只要按下复位开关，秒表都要无条件地进行复位操作，即使是在计时过程中也要无条件地进行清零操作。 设置启/停开关。当按下启/停开关后，将启动秒表输出，当再按一下启/停开关时，将终止秒表的输出。 采用结构化设计风格描述，即先设计一个10分频电路，再用此电路构建秒表电路。(Using Verilog to realize digital stopwatch (basic logic design frequency divider practice) Set the reset switch. When the reset switch is pressed, the stopwatch is zero and the timing is ready. In any case, as long as we press the reset switch, the stopwatch is unconditionally reset operation, even in the process of timing, we must do zero clearing operation without any conditions. Set up / stop switch. When the start / stop switch is pressed, the stopwatch output will be started. When the start / stop switch is pressed, the stopwatch output will be terminated. The structure design style is described, that is, first design a 10 frequency division circuit, then use this circuit to build a stopwatch circuit.)
Platform: | Size: 1024 | Author: VoidShooter | Hits:
« 12 3 4 5 6 7 »

CodeBus www.codebus.net