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Description: vhdl语言开发，开发环境为QuartusII6.0和NIOS 6.0开发，是一个模拟交通灯的程序，其中用的芯片是stratix系列-vhdl language development, QuartusII6.0 development environment for the development and NIOS 6.0, is a simulated traffic signals procedures, which the chip is stratix Series
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Size: 7180017 |
Author: 河南 |
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Description: vhdl语言开发，开发环境为QuartusII6.0和NIOS 6.0开发，是一个模拟交通灯的程序，其中用的芯片是stratix系列-vhdl language development, QuartusII6.0 development environment for the development and NIOS 6.0, is a simulated traffic signals procedures, which the chip is stratix Series
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Size: 7562240 |
Author: 河南 |
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Description: Verilog HDL: Magnitude
For a vector (a,b), the magnitude representation is the following:
A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm.
-Verilog HDL : For a vector magnitude (a, b), the magnitude representation is the following : A common approach to implementing thes e arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonome tric functions of sine, cosine, magn itude, and phase using an iterative process. It i 's made up of a series of micro-rotations of the v ector by a set of predetermined cons tants, which are powers of two. Using binary ar praxiology metic, this algorithm essentially replaces m ultipliers with shift and add operations. In a Stratix
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Size: 12288 |
Author: 郝晋 |
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Description: 这是一个fft的IP核，安装要求为quartus6.0以上。解压安装后可在quartus里例化使用，元件主要为cyclone和stratix,最大支持1024点的转换。
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Size: 8719360 |
Author: 李杰 |
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Description: 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure and the basic hardware features, a brief introduction of the FIR filter the way to achieve the advantages and disadvantages of combining Altera s Stratix series of characteristics of the product, with a MAC based on the 8-order FIR digital filter design For example, given the use of Verilog hardware description language for digital logic design process and methods, and Quartus Ⅱ integrated development environment, prepared HDL code, for comprehensive utilization of Quartus Ⅱ emulator internal design so the impulse response simulation and verification.
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Size: 79872 |
Author: sundan |
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Description: Altera公司高端FPGA高级综合指导手册，包括：算术运算单元，浮点处理技巧，数据编码格式转换，视频处理，仲裁逻辑，多路选择，存储逻辑，计数器，通信逻辑，循环冗余校验，随机和伪随机函数，加密和同步等编码风格和技巧；-advanced synthesis cookbook for Altera high-end FPGA(Stratix),incuding coding style and design tricks for
arithmetic,floating points operation,tranlation and format convertion,vidio, arbitor, multiplexing, registers and
memories,communication,CRC,random and pseudorandom functions,cryptography,synchronization,etc.
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Size: 962560 |
Author: 刘易 |
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Description: altera 公司 FPGA开发板原理图,核心芯片是stratix ii(主要用于DSP开发)-Company altera schematic FPGA development board, the core chip is stratix ii (mainly used for DSP development)
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Size: 523264 |
Author: 汪翔 |
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Description: myAltera的PCBLib库，包括Cyclone系列,Stratix系列，-myAlteraLib
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Size: 417792 |
Author: LaoY |
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Description: IMPLEMENTATION OF AN IEEE 802.11A TRANSMITTER IN VHDL FOR ALTERA STRATIX II FPGA
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Size: 244736 |
Author: bz |
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Description: 本文基于某制导雷达信号处理机优化改造工程，介绍了该雷达信号处理机的
接收相干处理(CORP)、动目标显示(MTI)的原理、硬件平台、软件设计、调试以及
优化设计方法。文章首先回顾了该信号处理机相关的信号处理方法，包括数字稳
定校正技术(DS功、参差周期滤波、多次相消器的动目标显示等方法的工作原理和
实现方式，并结合项目进行计算机仿真。其次介绍了信号处理机的组成结构，优
化设计思路，主要功能分配。最后重点讨论了信号处理机的各个模块的工程实现
方法以及数字信号处理器(TS201)存储器配置的优化。该雷达采用接收相干，参差
周期滤波及抗干扰技术，使用ALTERA公司的Stratix II系列芯片和高性能浮点数
字信号处理器ADSP TS201S构建信号处理机硬件平台，用VHDL，汇编语言和C
语言实现信号处理机的软件设计。结果表明，存储器配置的优化可以大大地提高
程序的执行效率，并且优化的总体设计方法可以在有限的硬件资源下提高系统的
实时性。-This paper is based on the optimization of data processor ofsome guidance radar．It is
introduced the design and implementation of the software and hardware of the
coherent-on-receive process(CORP)and moving target indicator(MTI)system，which
includes the debugging and optimizing processes ofboth software and hardware parts．
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Size: 2998272 |
Author: 123 |
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Description: Altera的I2C总线FPGA程序，内有详细使用说明- The I2C Controller is available in VHDL and is optimized for the Altera® APEX™ , Stratix® , and Cyclone™ device families.
All of the register addresses are defined as constants in the VHDL source files and can be easily customized for customer use. The MBASE address is defined as a generic and can also be easily changed and customized for customer use. In addition, this design outputs the MCF signal on a pin which can be used by the uC as a quick indication that the I2C transfer is complete.
This design uses the I2C SCL signal as a clock. This requires that the SCL signal have clean, fast edges on both the rising and falling edges of this signal. Slow rise and fall times on this signal can show noise effects which can cause improper clocking of registers within the Stratix FPGA. If the loading of the SCL signal in the system is such that the rise and fall times are slow (>20nS), external buffers such as Schmitt Triggers will be required to interface to the
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Size: 2252800 |
Author: 我是谁 |
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