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[VHDL-FPGA-Verilog] detector

Description:
Platform: | Size: 5120 | Author: 123 | Hits:

[VHDL-FPGA-Verilog] xljcq

Description: 用vhdl语言实现序列检测器的设计 这是学习VHDL语言的经典例子-Using VHDL language sequence detector design VHDL language learning this is a classic example of
Platform: | Size: 3072 | Author: 郭海东 | Hits:

[VHDL-FPGA-Verilog] detecter

Description: 这是序列检测器。串行序列产生是指根据时钟和相应的控制信号，产生稳定的单bit输出信号；监测器指根据相应时钟输入的电平序列，监测该序列中是否存在预设的序列，无论从第几个输入开始，只要存在，总能监测到。监测到予以标示。-This is the sequence detector. Have a serial sequence is defined as the clock and the corresponding control signal, producing a stable single-bit output signal monitor means the corresponding clock input sequence level, monitoring the sequence of the existence of the default sequence, whether from the first few enter a start, as long as there is, always monitored. Monitoring to be marked.
Platform: | Size: 101376 | Author: 徐芬 | Hits:

[VHDL-FPGA-Verilog] EDAdesign(3)

Description: 该文件中是关于一些VHDL许多编程实例以及源码分析，希望对VHDL爱好者有用。卷3包括车载DVD位控系统、直接数字频率合成器、图像边缘检测器、等精度数字频率计、出租车计费系统的设计与分析-The document is on a number of VHDL source code in many programming examples and analysis, in the hope that useful VHDL enthusiasts. Car DVD Volume 3 includes digital control system, direct digital frequency synthesizer, image edge detector, such as precision digital frequency meter, taxi Accounting System Design and Analysis
Platform: | Size: 4392960 | Author: shengm1 | Hits:

[VHDL-FPGA-Verilog] chk

Description: 本程序实现了一个序列检测器。当一串待检测的串行数据进入检测器后，若此数在每一位的连续检测中都与预置的密码数相同，则输出“A”,否则仍然输出“B”。-This procedure implements a sequence detector. When a string of serial data to be tested after entering the detector, if the number in each successive detection with the same number of preset password, then output A , otherwise the output is still B .
Platform: | Size: 1024 | Author: liushenshen | Hits:

[Communication-Mobile] E1_DCR

Description: 2MHz的数据时钟恢复电路，包括鉴相器、分频器及滤波器-2MHz data clock recovery circuit, including phase detector, divider and filter
Platform: | Size: 2048 | Author: Chen | Hits:

[VHDL-FPGA-Verilog] detect

Description: 一个序列检测器的设计。程序不是问题，关键是理解状态机的编程思想。-A sequence detector design. Procedure is not a problem, the key is to understand the thinking of state machine programming.
Platform: | Size: 1024 | Author: chengpan | Hits:

[VHDL-FPGA-Verilog] sequence_inspector

Description: 序列检测器可用于检测一组或多组二进制码组成的脉冲序列信号，这在数字通信领域中有广泛的应用。当序列检测器连续收到一组二进制码后，如果这组码与检测器中预先设置的码相同，则输出1，否则输出0。由于这种检测的关键在于正确码的收到必须是连续的，这就要求检测器必须记住前一次的正确码及正确序列，直到连续的检测中收到每一位都与预置数的对应码相同。在检测过程中，任何一位不相等都将回到初始状态重新开始检测。并附有测试程序-Sequence detector can be used to detect one or a binary code consisting of pulse sequence signal, which in the field of digital communications in a wide range of applications. When the sequence detector row received a group of binary code, if this group of codes and detectors in the same pre-set code, then output 1, otherwise output 0. As a result of this test lies in the receipt of the correct code must be continuous, which requires detector must be remembered that the previous code and correct the correct sequence, until the continuous detection and received every preset number of correspond to the same code. In the detection process, any one of unequal status will be returned to the initial detection of a fresh start. With test procedures
Platform: | Size: 1024 | Author: zhaohongliang | Hits:

[VHDL-FPGA-Verilog] JIANCHE

Description: 本设计是一个序列检测器，能够检测11位长的系列信号，根据需要可适当扩展其序列长度-The design is a sequence detector, can detect a long series of 11 signals, according to the needs may be appropriate to expand its sequence length
Platform: | Size: 342016 | Author: liuxiaozhong | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 要求用VHDL语言设计7人表决器和系列检测器，检测“1111111101111110”-VHDL language design requires a vote 7 and Series detector 1111111101111110
Platform: | Size: 1024 | Author: asd | Hits:

[Software Engineering] vhdl

Description: 包含VHDL语言设计7人表决器电路和系检测器列-VHDL language contains 7 to vote on the design of circuit and the Department of detector out
Platform: | Size: 2048 | Author: asd | Hits:

[Software Engineering] 111

Description: 数字鉴相器,数字锁相环频率合成系统FPGA的实现,很有借鉴价值-Digital phase detector, digital PLL frequency synthesizer system FPGA realization of referential value
Platform: | Size: 53248 | Author: 颜小山 | Hits:

[VHDL-FPGA-Verilog] seg_test

Description: 基于VHDL的序列检测器设计-VHDL-based sequence detector design
Platform: | Size: 156672 | Author: peter | Hits:

[Other] code

Description: 使用状态机设计一个5位序列检测器。从一串二进制码中检测出一个已预置的5位二进制码-The use of state machines to design a sequence detector 5. From a string of binary code to detect a preset binary code of 5
Platform: | Size: 48128 | Author: evelyn | Hits:

[VHDL-FPGA-Verilog] 2

Description: 序列检测器VHDL语言设计和仿真和校验模块的程序和仿真结果 -Sequence detector design and simulation of VHDL language and the validation process modules and simulation results
Platform: | Size: 38912 | Author: 林露吟 | Hits:

[ELanguage] EP1C3_81_SCHK

Description: 序列检测器设计 这里面是一个完整的工程可以直接适用-Sequence detector design there is a complete project can be applied directly
Platform: | Size: 7168 | Author: 小欧 | Hits:

[Other] ChargePumpPLL

Description: An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLL.pdf This paper investigates the design of passive loop filters for Frequency Synthesizers utilizing a Phase- Frequency Detector and a current switch charge pump.-An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLL.pdf This paper investigates the design of passive loop filters for Frequency Synthesizers utilizing a Phase-Frequency Detector and a current switch charge pump.
Platform: | Size: 129024 | Author: 刘洋 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 序列检测器设计VHDL源程序 任意输入串行数据串-VHDL source code sequence detector design arbitrary string of serial data input
Platform: | Size: 1024 | Author: terry | Hits:

[Other] detector

Description: 使用VHDL语言编写的用于检测某一序列的检测器-VHDL detector
Platform: | Size: 1024 | Author: zhangyu | Hits:

[VHDL-FPGA-Verilog] 用VHDL设计移位寄存器

Description: 实现序列检测，让你通过VHDL语言实现序列数字的发生(Sequence detector code)
Platform: | Size: 144384 | Author: 放飞的起航 | Hits:
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