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[Embeded-SCM Develop] moore

Description: Moore型状态机设计,基于VHDL.能够根据微处理器的读写周期,分别对应存储器输出写使能WE和读使能OE信号.-Moore-type state machine design, based on VHDL. Be able to read and write cycle of microprocessors, corresponding memory output enable WE write and read enable signal OE.
Platform: | Size: 25600 | Author: weixiaoyu | Hits:

[VHDL-FPGA-Verilog] SRAM-PINGPANG

Description: 超声视频图像需要实时地采集并在处理后在显示器上重建，图像存储器就必须不断地写入数据，同时又要不断地从存储器读出数据送往后端处理和显示[11]。为了满足这种要求，可以在采集系统中设置2片容量一样的SRAM，通过乒乓读写机制来管理。任何时刻，只能有1片SRAM处于写状态，同时也只有1片SRAM处于读状态。工作期间，2片SRAM都处于读写状态轮流转换的过程，转换的过程相同，但是状态错开，从而保证数据能连续地写人和读出祯存.-Real-time ultrasound video images need to collect and deal with the reconstruction after the display, image memory must be continually write data, while at the same time continuously sent from the memory读出数据back-end processing and display [11]. To meet this requirement, you can set up collection system capacity of two different SRAM, read and write through the ping-pong mechanisms to manage. At any time, can only have a SRAM in write state, but also the only one at a time the state of SRAM. Work, two SRAM read and write are in the process of converting a state of rotation, the conversion process of the same, but the state staggered to ensure that data can be continuously written and read out Qizhen depositors.
Platform: | Size: 1024 | Author: smj1980 | Hits:

[VHDL-FPGA-Verilog] uriscram

Description: RAM存储器： 设定16 个8 位存储单元。如果read= 1 则dataout<=mem(conv_integer(address)). 如果write= 1 则mem(conv_integer(address))<=datain. -RAM memory: Set 16 8 memory cell. If read = 1 is dataout
Platform: | Size: 1024 | Author: 良芯 | Hits:

[VHDL-FPGA-Verilog] ram

Description: 存储器模块生成，采用16位数据总线，5位读写地址总线，异步清零！-Memory modules generated, using 16-bit data bus, 5 to read and write address bus, asynchronous Clear!
Platform: | Size: 2048 | Author: 齐磊 | Hits:

[VHDL-FPGA-Verilog] pci_t

Description: verilog开发的PCI target模块，能完成配置空间的读写以及单次的memory读写，原创。-Verilog development of PCI target module, to complete the reading and writing, as well as the configuration space of a single memory read and write, originality. Ha ha
Platform: | Size: 10240 | Author: 齐培红 | Hits:

[Embeded-SCM Develop] r_w_flash

Description: FPGA高速完成AD采集回来的数据进行高速读写FLASH存储-AD Acquisition completion of FPGA high-speed data back to high-speed read and write FLASH memory
Platform: | Size: 901120 | Author: 王瓶 | Hits:

[Communication-Mobile] wb_lpc_latest.tar

Description: Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided. None of this has been tested (yet) with a third-party LPC Peripheral or Host.
Platform: | Size: 410624 | Author: Arun | Hits:

[VHDL-FPGA-Verilog] rom

Description: 只读存储器VHDL代码，可运行实现，已用quartusII6.0验证-Read-only memory VHDL code can be run to achieve has been used to verify quartusII6.0
Platform: | Size: 1024 | Author: 干璐 | Hits:

[FlashMX] readandwrite

Description: 三星k9系列flash memory读写程序-K9 Series Samsung flash memory to read and write procedures
Platform: | Size: 2048 | Author: 晓婕 | Hits:

[Windows Develop] cpu16

Description: 实现一个16位CPU。该CPU使用精减指令集，是一个五段流水线的结构。包括取指令(IF)、读寄存器(RD)、运算器(ALU)、内存读写(MEM)和写回(WB)。-The realization of a 16-bit CPU. Streamline the use of the CPU instruction set is a structure of five lines. Including fetch (IF), register read (RD), arithmetic logic unit (ALU), memory read and write (MEM) and Write Back (WB).
Platform: | Size: 6144 | Author: 周健 | Hits:

[OS program] jtag

Description: JTAG Tools is a software package which enables working with JTAG-aware (IEEE 1149.1) hardware devices (parts) and boards through JTAG adapter. This package has open and modular architecture with ability to write miscellaneous extensions (like board testers, flash memory programmers, and so on). JTAG Tools package is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. There is absolutely no warranty for JTAG Tools. Please read COPYING file for more info. -JTAG Tools is a software package which enables working with JTAG-aware (IEEE 1149.1) hardware devices (parts) and boards through JTAG adapter. This package has open and modular architecture with ability to write miscellaneous extensions (like board testers, flash memory programmers, and so on). JTAG Tools package is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. There is absolutely no warranty for JTAG Tools. Please read COPYING file for more info.
Platform: | Size: 957440 | Author: asdf | Hits:

[VHDL-FPGA-Verilog] flash

Description: fpga的FLASH读写VERILOG代码。希望对大家有用-the verilog code of fpga read/write flash
Platform: | Size: 1024 | Author: Denny | Hits:

[Other] sram

Description: to write and read from an sram. its actually a logic cell,when the write enable is high its possible to write data onto a memory location when read enable is high we can read the data in given memory location
Platform: | Size: 37888 | Author: mariamma | Hits:

[VHDL-FPGA-Verilog] LPC2DDR2

Description: Module Function Description: This module allows a SPI ROM to be used in a LX/CS5536 system. Details are below: 1.Provide a memory window to the SPI EPROM at FFF80000h-FFFFFFFFh (512KB). 2.Provide an interface to the SPI bus to allow the SPI EPROM to be programmed. 3.Support DDR2 memory initial process. 4.Support LPC/SPI ROM switch using Hardware pin selection and Software setting method 5.Support LPC Memory Read/Write, LPC I/O Read/Write 6.Support SPI Chip Erase/Byte Program/Write Status/Read Status/Read Array -Module Function Description: This module allows a SPI ROM to be used in a LX/CS5536 system. Details are below: 1.Provide a memory window to the SPI EPROM at FFF80000h-FFFFFFFFh (512KB). 2.Provide an interface to the SPI bus to allow the SPI EPROM to be programmed. 3.Support DDR2 memory initial process. 4.Support LPC/SPI ROM switch using Hardware pin selection and Software setting method 5.Support LPC Memory Read/Write, LPC I/O Read/Write 6.Support SPI Chip Erase/Byte Program/Write Status/Read Status/Read Array
Platform: | Size: 8192 | Author: 吴羽中 | Hits:

[VHDL-FPGA-Verilog] ddr2_controller

Description: DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.
Platform: | Size: 52224 | Author: yanxp | Hits:

[Software Engineering] OneNAND_in_embed_sys

Description: OneNAND闪存在嵌入式系统中的应用 OneNAND Flash是三星公司开发的一类Flash芯片，它克服了传统NAND Flash接口复杂的缺点，具有接口简单、读写速度快、容量大、寿命长、成本低等优点。文章从软硬件两方面介绍了其在嵌入式系统中的应用，特别是逻辑块和物理块地址的映射、读写擦操作、坏块处理、性能优化等技术。-OneNAND flash memory in embedded system applications developed by Samsung' s OneNAND Flash is a type Flash chips, which overcomes the traditional shortcomings of NAND Flash interface, a complex with a simple interface, read and write speed, large capacity and long life and low cost advantages. The article describes both hardware and software in embedded system applications, in particular logical block and physical block address mapping, read and write wiping operation, bad block handling, performance optimization technologies.
Platform: | Size: 48128 | Author: zhangdong | Hits:

[VHDL-FPGA-Verilog] led_control

Description: 本实验箱采用的液晶显示屏内置的控制器为SED1520，点阵为122×32，需要两片SED1520组成，由E1，E2分别选通，以控制显示屏的左右两半屏。图形液晶显示模块有两种连接方式，一种为直接访问方式，一种为间接访问方式。本实验采用直接控制方式。 直接控制方式就是将液晶显示模块的接口作为存储器或I/O设备直接挂在计算机总线上。计算机通过地址译码器控制E1和E2的选通；读/写操作信号R/W有地址线A1 控制，命令/数据寄存器选择信号由地址线A0控制。 -The experimental box with built-in LCD controller for the SED1520, lattice is 122 × 32, needs two SED1520 formed by the E1, E2, respectively gating to control the display of about two and a half screen. Graphic LCD module has two connections, one for the direct access method, an indirect access. In this study the direct control mode. Direct control method is to interface LCD module as memory or I/O devices directly linked to the computer bus. Computer controlled by address decoder strobe E1 and E2 read/write signal R/W control the address lines A1, command/data register select control signal from the address line A0.
Platform: | Size: 1206272 | Author: yangxiao | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 设计以及基本的CPU，至少包括四个基本单元，控制单元，内部寄存器，ALU和指令集-The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its performance. For simplicity, we will only consider the relationship among the CPU, registers, memory and instruction set. That is to say we only need consider the following items: Read/Write Registers, Read/Write Memory and Execute the instructions. At least four parts constitute a simple CPU: the control unit, the internal registers, the ALU and instruction set, which are the main aspects of our project design and will be studied.
Platform: | Size: 2196480 | Author: mollyma | Hits:

[VHDL-FPGA-Verilog] xapp944_source

Description: 主要用来实现FPGA控制nand flash存储器的读写控制，是公司网站提供-FPGA is mainly used to achieve control of read and write nand flash memory control, is the company website
Platform: | Size: 1140736 | Author: lijin | Hits:

[VHDL-FPGA-Verilog] Audio_Reader_Flash_DE2

Description: This an DE2 card software, which is able to read some Audio file from a memory (Flash for example). Extendable to read from a SD card, and to write on it.-This is an DE2 card software, which is able to read some Audio file from a memory (Flash for example). Extendable to read from a SD card, and to write on it.
Platform: | Size: 76800 | Author: Minimus | Hits:
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