Description: 一些很实用的verilog源程序，是初学者的好棒手，希望能给需要的人一点帮助，请支持一下。-some very practical Verilog source is the beginners excellent hands, in hopes of giving those who need a bit of help, please support what. Platform: |
Size: 165888 |
Author:叶若寒 |
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Description: 本程序功能:
DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频.
可通过键盘操作设置频率参数和选择波形种类和控制运行.
由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-this program functions : DDS folder procedures, complete direct digital frequency synthesis, sine, triangle, Three square waveform, and can sweep. can be set up through the keyboard operation frequency waveform parameters and the types of choice and control operations. composed of two parts, "C" folder, for the 51 microcontroller running C Programming Language, "Verilog" folder, use the Verilog language FPGA procedures. Platform: |
Size: 1027072 |
Author:吴健 |
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Description: 基于ｆｐｇａ，采用ｑｕａｒｔｕｓ２的ＤＤＳ信号发生器，采用高速ＤＡＣ９０８为数模芯片，并可通过５１单片机送入调制信号进行ＦＭ调制-Based on the fpga, the use of the DDS signal generator quartus2 using DAC908 number of high-speed chip module, and passed into 51 single-chip FM modulation signal modulation Platform: |
Size: 2745344 |
Author:张新 |
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Description: Verilog实现的DDS正弦信号发生器和测频测相模块，DDS模块可产生两路频率和相位差均可预置调整的值正弦波，频率范围为20Hz-5MHz，相位范围为0°-359°，测量的数据通过引脚传输给单片机，单片机进行计算和显示。-Verilog realize the DDS sine wave signal generator and frequency measurement module test phase, DDS module can generate both frequency and phase difference can be preset to adjust the value of sine wave, frequency range of 20Hz-5MHz, phase range of 0 °-359 ° , measurement data and transmit them to the single-chip pin, single-chip microcomputer to calculate and display. Platform: |
Size: 1371136 |
Author:haoren |
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Description: FPGA中实现基于查找表方式（LUT）的DDS实现，可用在数字下变频和COSTAS锁相环中，Verilog编写，本人已经调通-In FPGA-based lookup table approach (LUT) to achieve the DDS can be used in the digital down-conversion and COSTAS PLL, Verilog prepared, I have transferred Qualcomm Platform: |
Size: 148480 |
Author: |
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Description: 基于DDS原理的正弦信号发生器。用VERILOG语言实现，功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful. Platform: |
Size: 558080 |
Author:毛华站 |
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Description: FPGA内AM调制工程。内带调制波、载波生成。关键词：FPGA verilog AM DDS-AM modulation works within the FPGA. Within the band modulation wave generated carrier. Key words: FPGA verilog AM DDS Platform: |
Size: 1687552 |
Author:baixiangzhou |
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Description: 关于FPGA中DDS核参数设置的资料，英文版的XILINX资料-DDS on the FPGA in the data set of nuclear parameters, the English version of XILINX information Platform: |
Size: 1664000 |
Author:李晶 |
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Description: 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency Platform: |
Size: 190464 |
Author:赵一 |
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Description: 基于Verilog的dds设计，已经经过调试，可直接使用-Dds of Verilog-based design, has been testing can be used directly Platform: |
Size: 2041856 |
Author:郭帅 |
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Description: FPGA控制AD9854的源文件，verilog，附有简单文档。-FPGA to control the AD9854 source file, verilog, with a simple document. Platform: |
Size: 820224 |
Author:柴佳 |
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Description: 在FPGA内，以查表方式实现频率直接合成器（DDS）功能。verilog源代码-In the FPGA in order to achieve the look-up table means the direct synthesizer frequency (DDS) feature. verilog source code Platform: |
Size: 2048 |
Author:niuqs |
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Description: DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频.
可通过键盘操作设置频率参数和选择波形种类和控制运行.
由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-DDS program folder, complete direct digital frequency synthesis function, sine, triangle, square wave three, and can sweep. Can be set by keyboard operation frequency parameters and select the waveform type and control operation. Consists of two parts, " C" folder, is used to running on the microcontroller in the 51 C language program, " Verilog" folder, is written in Verilog FPGA program. Platform: |
Size: 433152 |
Author:王金 |
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