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[VHDL-FPGA-Verilog] entropy_coding

Description: 用verilog 描述的嫡编码(entropy coding) 应用于图像压缩编码 有测试文档 -using Verilog His description of coding (entropy coding) for image compression test files are encoded
Platform: | Size: 19456 | Author: 周信均 | Hits:

[Graph program] sobel

Description: 图像边缘检测的VERILOG实现，能准确检测图像边缘-Image Edge Detection of Verilog realize that can accurately detect image edge
Platform: | Size: 589824 | Author: 李永杰 | Hits:

[VHDL-FPGA-Verilog] tb

Description: 检测上升沿的verilog程序，有验证程序，可用synplify验证-Detection of rising edge of the Verilog procedures, there is the verification process can be used to verify Synplify
Platform: | Size: 1024 | Author: ly | Hits:

[VHDL-FPGA-Verilog] edge_detection

Description: edge detection algorithm in verilog HDL, along with test bench file. compiled in modelsim6.1
Platform: | Size: 34816 | Author: yahyajan | Hits:

[VHDL-FPGA-Verilog] sobel

Description: verilog sobel FPGA edge detection-Adopted verilog language realizes sobel edge detection in image processing algorithm
Platform: | Size: 10240 | Author: wkd | Hits:

[VHDL-FPGA-Verilog] Edge-detection

Description: 多个边缘检测sobel算子的verilog程序模块。-Multiple edge detection sobel operator verilog program modules
Platform: | Size: 4096 | Author: | Hits:

[VHDL-FPGA-Verilog] motor_PWM

Description: 刚写的verilog 程序，控制直流电机正反转，具有严格的按键消抖函数，采用脉冲边沿检测法，防止误触发！-Just write verilog program to control the DC motor reversing, with strict key debounce function, pulse edge detection method, to prevent false triggering! ! ! Beginner EDA, if insufficient, please correct me! ! !
Platform: | Size: 303104 | Author: 谷向前 | Hits:

[VHDL-FPGA-Verilog] verilog2

Description: 用verilog语言编写的按键消抖程序。通过下降沿检测法可以判断出是否按键。压缩包内也包含此按键消抖程序的modelsim仿真文件。-Verilog language with key debounce process. By falling edge detection method can determine whether the key. This compressed package also contains procedures for key debounce modelsim simulation files.
Platform: | Size: 183296 | Author: 广子 | Hits:

[VHDL-FPGA-Verilog] edge_tech_design

Description: verilog的边沿检测技术，在fpga信号处理中应用相当的大,这也是一门艺术-the the verilog edge detection technology, in fpga signal processing is quite large, and this is an art
Platform: | Size: 37888 | Author: 磨国钰 | Hits:

[VHDL-FPGA-Verilog] edg_test_design

Description: 边沿检测电路的程序，对于学习FPGA的语言非常重要，采用verilog语言编写。-Edge detection circuit program is very important for language learning FPGA using Verilog language.
Platform: | Size: 308224 | Author: zhaorongjian | Hits:

[Other] edge-test

Description: Verilog HDL边沿检测主要有上升沿和下降沿检测-Verilog HDL edge detection are rising and falling edge detection
Platform: | Size: 295936 | Author: 阿呆 | Hits:

[Other] sobel-with-verilog-language

Description: 用verilog实现sobel边缘检测算法-sobel edge detection with verilog language
Platform: | Size: 8192 | Author: 施楠 | Hits:

[VHDL-FPGA-Verilog] Posedge-Detection-Circuit

Description: Verilog脉冲边沿检查，此代码包含完整的工程，利用quartus软件可以直接运行仿真。-Verilog edge of pulse examination, this code contains the complete engineering, quartus software can be used to directly run the simulation.
Platform: | Size: 3117056 | Author: 张林 | Hits:

[ELanguage] MDL_SLX

Description: sobel edge detection using verilog code
Platform: | Size: 18432 | Author: ANDREW DENI X G | Hits:

[VHDL-FPGA-Verilog] edge-detection1

Description: 基于FPGA开发环境，根据Sobel model算法，关于边缘检测的verilog代码。-the code of edge detection based on verilog.
Platform: | Size: 1024 | Author: Oscar | Hits:

[VHDL-FPGA-Verilog] sw_debounce

Description: 脉冲边沿检测法的按键消抖程序，使用Verilog编写(Key edge dithering program with pulse edge detection method)
Platform: | Size: 4425728 | Author: 水白三千 | Hits:

[Other] Edge Detection Filters

Description: Edge Detection Filters
Platform: | Size: 508928 | Author: ssaeed | Hits:

[VHDL-FPGA-Verilog] Verilog的边沿检测技术_设计源代码

Description: 波形数据上升下降沿的检测程序，已经经过仿真验证(The detection program of the rising descending edge of the waveform data has been verified by simulation)
Platform: | Size: 36864 | Author: gxgone | Hits:

[VHDL-FPGA-Verilog] VIP_RAW2RGB2Gray_Medium_Sobel_Erosion_Dilation

Description: 通过纯HDL逻辑实现,对ov7725摄像头进行图像采集,存储,处理,包括中值滤波,边缘检测等经典图像算法实现(Through the realization of pure HDL logic, image acquisition, storage and processing of ov7725 camera, including median filtering, edge detection and other classic image algorithms.)
Platform: | Size: 931840 | Author: SakuraForever | Hits:

[VHDL-FPGA-Verilog] sobel

Description: 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)
Platform: | Size: 10222592 | Author: 丶大娱乐家 | Hits:
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