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[Communication] verilog for uart

Description: 通用异步接收器/发送器(UART)是能够编程以控制计算机到附加串行设备的接口的微芯片。详细来说,它提供给计算机RS-...还有高级的UART提供了一定数量的数据缓冲,这样计算机和串行设备数据流就可以保持同样的速度。-universal asynchronous receiver/transmitter (UART) can be programmed to control computer attached to the serial device interface microchips. Details, provide it to the computer RS-High ... UART also provide a certain number of data buffer, computer equipment and serial data stream can maintain the same speed.
Platform: | Size: 9216 | Author: 李志 | Hits:

[VHDL-FPGA-Verilog] uart-verilog-vhdl

Description: 拿verilog和vhdl编写的串口通信代码(可综合)-with vhdl and verilog prepared by the serial communication code (synthesis)
Platform: | Size: 294912 | Author: 刘索山 | Hits:

[VHDL-FPGA-Verilog] serial

Description: VerilogHDL例程，实现和PC机进行基本的串口通信。-VerilogHDL routine, and realize the basic PC-to serial communication.
Platform: | Size: 67584 | Author: xuping | Hits:

[VHDL-FPGA-Verilog] uart

Description: 用Verilog实现的串口异步通信，适用于RS232-Using Verilog realization of serial asynchronous communication, applied to RS232
Platform: | Size: 1126400 | Author: 王权 | Hits:

[VHDL-FPGA-Verilog] UART_rec

Description: verilog 串口接收程序，在ACTEL Fusion FPGA上实验成功 和大家一起分享！^_^-Verilog serial receive process, ACTEL Fusion FPGA in the experimental success and share with everyone! ^ _ ^
Platform: | Size: 1024 | Author: whq | Hits:

[VHDL-FPGA-Verilog] uart(Verilog)

Description: uart异步串口通信协议的源代码，用vhdl语言编写，并且有完整得测试文件-UART asynchronous serial communication protocol source code, using VHDL language, and may have a complete test file
Platform: | Size: 10240 | Author: 阿军 | Hits:

[Other Embeded program] seqdet

Description: 对串行输入的数据流进行检测的ＶＥＲＩＬＯＧ源代码-On the serial input data streams to detect the Verilog source code
Platform: | Size: 18432 | Author: 刘建明 | Hits:

[VHDL-FPGA-Verilog] A_bit_serial_data_transmitter

Description: 比特序列传送模块 把输入的八位比特数据 做循环后每个比特输出 详细请看英文描述-• To create Verilog-HDL modules written in the RTL style appropriate for both simulation and synthesis, for the various component parts of an Asynchronous Serial Data Transmitter. • To verify the correct behaviour of each component part by means of simulation. • To construct a top-level module corresponding to the Asynchronous Serial Data Transmitter, making use of the component parts developed above, and any additional behavioural elements which may be required. • To verify the correct operation of the top-level design by means of simulation using a Verilog-HDL test-fixture. • To automatically create a hierarchical logic diagram for the Asynchronous Serial Data Transmitter, generated using a Logic Synthesis tool.
Platform: | Size: 2048 | Author: 吴德昊 | Hits:

[Com Port] RS232

Description: 很好用的串口通讯程序，已经通过验证，用Verilog语言编写的放心使用了！-Good use of serial communication program has been validated using Verilog language used in the rest assured!
Platform: | Size: 54272 | Author: 宋振丰 | Hits:

[Parallel Port] cw3

Description: serial port rs232 in verilog source code
Platform: | Size: 1024 | Author: malkanin | Hits:

[SCM] signal

Description: verilog写的串口控制信号发生器，能通过用串口控制产生正弦波方波等信号-written in verilog serial control signal generator, can be generated using serial control, such as sine wave square wave signals
Platform: | Size: 5519360 | Author: ray | Hits:

[VHDL-FPGA-Verilog] uart

Description: This Verilog file is a desription of an UART, which is a piece of computer hardware that translates data between parallel and serial forms.
Platform: | Size: 1024 | Author: Balazs Jozsa | Hits:

[VHDL-FPGA-Verilog] verilog.DA.FIR..

Description: 用verilog写的16阶串行DA算法FIR滤波器-Verilog written by 16-order FIR filter serial DA algorithm
Platform: | Size: 576512 | Author: 代鑫 | Hits:

[Communication-Mobile] Serial

Description: 串口通讯程序，用的芯片是 CP2102， Verilog HDL 程序，编译通过，完全可用-Serial communications program, using chip CP2102, Verilog HDL program, compiled by completely available
Platform: | Size: 112640 | Author: Li xiaohu | Hits:

[Other] Verilog

Description: 该代码是Veriloghdl语言实现的串口通信，经过FPGA板子下载验证通过，读者可以使用-The code is Veriloghdl language of the serial communications, after verification by FPGA board download, readers can use
Platform: | Size: 194560 | Author: 雪晨 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 一个很好的关于verilog的PPT 第1章 EDA设计与Verilog HDL语言概述 第2章 Verilog HDL基础与开发平台操作指南 第3章 Verilog HDL程序结构 第4章 VERILOG HDL语言基本要素 第5章 面向综合的行为描述语句 第6章 面向验证和仿真的行为描述语句 第7章 系统任务和编译预处理语句 第8章 VERILOG HDL可综合设计的难点解析 第9章 高级逻辑设计思想与代码风格 第10章 可综合状态机开发实例 第11章 常用逻辑的VERILOG HDL实现 第12章 XILINX硬核模块的VERILOG HDL调用 第13章 串口接口的VERILOG HDL设计-A good verilog of PPT on Chapter 1 of EDA Design and Verilog HDL language outlined in Chapter 2 based on Verilog HDL and development platform Operations Guide Chapter 3 Verilog HDL program structure VERILOG HDL languages Chapter 4 Chapter 5 for the basic elements of an integrated behavioral description statement in Chapter 6 for the verification and simulation of the behavior of the system described in Chapter 7 mission statements and prepared statements compiled in Chapter 8 VERILOG HDL design can be integrated Difficulties in Chapter 9, advanced logic design and coding style Chapter 10 Comprehensive state machine instance can be developed in Chapter 11 to achieve common logic VERILOG HDL Chapter 12 XILINX hard core module VERILOG HDL called Chapter 13 Serial Interface VERILOG HDL design
Platform: | Size: 27825152 | Author: lyy | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 第1章 EDA设计与Verilog HDL语言概述 第2章 Verilog HDL基础与开发平台操作指南 第3章 Verilog HDL程序结构 第4章 VERILOG HDL语言基本要素 第5章 面向综合的行为描述语句 第6章 面向验证和仿真的行为描述语句 第7章 系统任务和编译预处理语句 第8章 VERILOG HDL可综合设计的难点解析 第9章 高级逻辑设计思想与代码风格 第10章 可综合状态机开发实例 第11章 常用逻辑的VERILOG HDL实现 第12章 XILINX硬核模块的VERILOG HDL调用 第13章 串口接口的VERILOG HDL设计-Chapter 1 of the EDA Design and Verilog HDL language outlined in Chapter 2 based on Verilog HDL and development platform Operations Guide Chapter 3 Verilog HDL program structure VERILOG HDL languages Chapter 4 Chapter 5 of the basic elements for a comprehensive statement in Chapter 6 describe the behavior of surface and simulation to verify the behavior of the system described in Chapter 7 mission statements and prepared statements compiled in Chapter 8 VERILOG HDL design can be integrated Difficulties in Chapter 9, advanced logic design and coding style Chapter 10 to develop an integrated state machine instance 11 Common logic VERILOG HDL Chapter Chapter 12 XILINX to achieve hard-core module VERILOG HDL called Chapter 13 Serial Interface VERILOG HDL design
Platform: | Size: 27831296 | Author: lyy | Hits:

[VHDL-FPGA-Verilog] uartTransceiver

Description: Verilog Serial port
Platform: | Size: 1024 | Author: Kemper | Hits:

[VHDL-FPGA-Verilog] Verilog-Serial-communication

Description: Verilog在DE2实现串口通信，通过上位机给DE2发送数据，并反馈给上位机-Verilog serial communication in the DE2 DE2 send data through the host computer, and feedback to the host computer
Platform: | Size: 34816 | Author: Mr.wang | Hits:

[VHDL-FPGA-Verilog] Uart-Verilog

Description: verilog实现串口通讯，包括verilog代码和testbench代码(verilog serial communication, including the verilog code and testbench Code)
Platform: | Size: 791552 | Author: 代工 | Hits:
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