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[Other resource] yunsuan-verilog

Description: 运算器的实现，即实验指导书中的实验一，文件中包含有原代码及端口设置（可变），用vrilog HDL编程，Xilinx ISE 6仿真，并在实际电路中得到实现．-operations for the realization of the experimental guidance of a book. document contains the original code and port settings (variable), with vrilog HDL programming, Xilinx ISE 6 simulation, and the actual circuit realization.
Platform: | Size: 1600570 | Author: 王越 | Hits:

[Other resource] trafficLight-verilog

Description: 交通灯状态机的实现，用verilog HDL编程，Xilinx ISE 6仿真，在实际电路中得到验证．-traffic lights to achieve the state machine, with verilog HDL programming, Xilinx ISE 6 simulation, the actual circuit have been tested.
Platform: | Size: 1533527 | Author: 王越 | Hits:

[SourceCode] verilog dpll（数字锁相环）

Description: 用xilinx ise 10.1实现了数字锁相环，仅供参考
Platform: | Size: 667591 | Author: ronglijun@gmail.com | Hits:

[VHDL-FPGA-Verilog] VerilogHDLPLI

Description: Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii or modelsim simulation,
Platform: | Size: 1024 | Author: 杨锐 | Hits:

[Other Embeded program] yunsuan-verilog

Description: 运算器的实现，即实验指导书中的实验一，文件中包含有原代码及端口设置（可变），用vrilog HDL编程，Xilinx ISE 6仿真，并在实际电路中得到实现．-operations for the realization of the experimental guidance of a book. document contains the original code and port settings (variable), with vrilog HDL programming, Xilinx ISE 6 simulation, and the actual circuit realization.
Platform: | Size: 1600512 | Author: 王越 | Hits:

[Other Embeded program] trafficLight-verilog

Description: 交通灯状态机的实现，用verilog HDL编程，Xilinx ISE 6仿真，在实际电路中得到验证．-traffic lights to achieve the state machine, with verilog HDL programming, Xilinx ISE 6 simulation, the actual circuit have been tested.
Platform: | Size: 1532928 | Author: 王越 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 自己编写的一个verilog时钟程序，在xilinx的ISE仿真通过-I have written a Verilog clock procedures, in Xilinx s ISE simulation through
Platform: | Size: 327680 | Author: lg | Hits:

[VHDL-FPGA-Verilog] task_function

Description: 自己编写的一个verilog HDL小程序，实现基本的task调用function的功能，对初学者有用。在xilinx的ISE仿真调试通过-I have written a verilog HDL small procedures, to achieve the basic function of the task to call the function, useful for beginners. In Xilinx s ISE simulation debugging through
Platform: | Size: 235520 | Author: lg | Hits:

[VHDL-FPGA-Verilog] ISE_chinese_user_guide

Description: Xilinx—ISE的中文使用说明，写的很简单，但对于入门者很实用。看过市面上很多Xilinx的书，发现很多都是在这本书的基础上稍加改写，。
Platform: | Size: 915456 | Author: joan | Hits:

[VHDL-FPGA-Verilog] ISE_assistant_design_tool

Description: Xilinx－ISE辅助设计工具的中文使用说明，包括IP核生成器，布局布线器，FPGA底层编辑器，时序分析器，集成化逻辑分析工具，功率分析工具-Xilinx-ISE-aided design tools for use in Chinese, including the IP core generator, layout router, FPGA Editor bottom, timing analyzer, integrated logic analysis tools, power analysis tools
Platform: | Size: 1589248 | Author: joan | Hits:

[VHDL-FPGA-Verilog] vgaFPGA

Description:
Platform: | Size: 333824 | Author: bluefeifei | Hits:

[VHDL-FPGA-Verilog] ADC0832_test

Description: ADC0832是一个8-bit的ADC转化芯片，工作频率为250Khz，最大频率可达400Khz，转化通道有两个，输入电压可分有单端或差分形式。本测试使用单端电压输入形式，从昔年的CH0输入电压，使用Xilinx XC3S200AN开发板，并且使用Xilinx ise工具中的ChipScope工具来查看转化后的DO数据是否正确。经验证，输入电压范围是0V--5.5V,当电压达到5.5V时，满刻度.-ADC0832 is an 8-bit conversion of the ADC chip, the working frequency of 250Khz, the maximum frequency of up to 400Khz, into two channels, the input voltage can be divided into single-ended or differential form. This test used the form of single-ended voltage input, from the previous years of the CH0 input voltage, the use of Xilinx XC3S200AN development board, Xilinx ise tools and use of ChipScope tool to see into the post-DO data is correct. Validated, input voltage range is 0V- 5.5V, when the voltage reaches 5.5V, the full-scale.
Platform: | Size: 3628032 | Author: zhangjiansen | Hits:

[VHDL-FPGA-Verilog] Multiplier

Description: It s a design of a 4*4 multiplier based on Verilog, using Xilinx ISE.
Platform: | Size: 859136 | Author: wayne | Hits:

[Other Embeded program] Receiver

Description: 基于802.11a的OFDM基带硬件设计的verilog代码，在Xilinx ISE环境下实现-The OFDM-based 802.11a baseband hardware design of the verilog code, in the Xilinx ISE environment to achieve
Platform: | Size: 2328576 | Author: 肖夜 | Hits:

[VHDL-FPGA-Verilog] CFO_Correction

Description: 载波频率同步Verilog程序 基于xilinx ise 实现-Carrier frequency synchronization Verilog program is based on xilinx ise to achieve
Platform: | Size: 412672 | Author: sunk | Hits:

[VHDL-FPGA-Verilog] Processor_alu

Description: this Code is in verilog HDL. This Code is for piplined processor with 4 opcode. this will work in three cycle latch, decode and exicute.. test bench for xilinx ise is laos given
Platform: | Size: 4096 | Author: Yogesh PAtel | Hits:

[VHDL-FPGA-Verilog] A8255V4

Description: A8255.ZIP contains code that implement a modified 8255 Peripherial Port Controller. The code is written in verilog and project is made for XILINX ISE.
Platform: | Size: 540672 | Author: asimlink | Hits:

[VHDL-FPGA-Verilog] Verilog-Design

Description: 包括三个文档: 1.基于Altera Quartus II 的模块化设计应用 2.基于Xilinx ISE的的模块化设计示例 3.模块化设计方法的设计流程-Consists of three documents: 1. Based on Altera Quartus II modular design applications 2. Xilinx ISE based on the modular design of Example 3. Modular Design for design process
Platform: | Size: 252928 | Author: Joseph | Hits:

[VHDL-FPGA-Verilog] ise_book

Description: Xilinx公司推荐FPGA培 训教材Xilinx ISE 9.xFPGA/CPLD设计指南的配套光盘内容，每个程序含verilog和VHDL两具版本-Training materials recommended by Xilinx Xilinx ISE 9.xFPGA/CPLD FPGA design guidelines supporting the CD content, each program contains two versions of verilog and VHDL
Platform: | Size: 8774656 | Author: 王建伟 | Hits:

[VHDL-FPGA-Verilog] Verilog led

Description: Xilinx ISE开发平台实现4位的led灯循环点亮源代码，测试文件及约束(4 bit LED lamp cycle lighting)
Platform: | Size: 29696 | Author: 韩么韩 | Hits:
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