Search - alarm clock vhdl

[VHDL-FPGA-Verilog] 多功能电子钟

Description: 具有多种功能的电子钟：闹钟，报时和修改，定时闹钟，报时时间，带闹钟，报时开关。-with multiple functions of electronic bell : alarm clock, timer and modification, regular alarm clock, timer, with alarm clock, timer switches.
Platform: | Size: 6144 | Author: 张建 | Hits:

[VHDL-FPGA-Verilog] time_display&alarm_clock

Description: 此为在实验板上通过的时钟闹铃程序，源码分别用ASM和VHDL描叙，但两程序功能不同。-this experiment for the board through the alarm clock procedures were used ASM source VHDL and depicts, but the two procedures different functions.
Platform: | Size: 2048 | Author: 陈谷 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 用VHDL语言编写的一个闹钟程序，可以整点报时，设置时间，设置闹钟。-VHDL language using an alarm clock to prepare procedures, can be the whole point of time, set time, set an alarm clock.
Platform: | Size: 768000 | Author: zhg | Hits:

[Other systems] clock_VHDL

Description: VHDL设计的数字时钟，有闹钟、整点报时等功能-VHDL design of the digital clock has an alarm clock, the whole point timekeeping functions
Platform: | Size: 510976 | Author: 王毅诚 | Hits:

[Software Engineering] clock

Description: 基于vhdl的数字钟有闹钟,秒表,时钟,日期等功能秒表可以开始,暂停,清零, 时钟可以设置时间, 还可以设置日期-VHDL based on the digital clock has an alarm clock, stopwatch, clock, date, stopwatch functions can start, pause, cleared, the clock can be set-up times, you can set the date
Platform: | Size: 3072 | Author: 张廷 | Hits:

[Other] C2

Description: 功能更加完善的基于vhdl的数字时钟设计有秒表，时钟，时期，闹钟的功能和整点报时，时间调整，日期调整，闹钟的设定、、、、、、、秒表有开始，暂停，清零等功能，且只有在暂停的情况下才能清零。-Function more complete VHDL-based design of the digital clock stopwatch, clock, time, alarm clock function and the whole point timekeeping, time adjustment, date, alarm clock settings ,,,,,,, stopwatch has started, pause, Clear and other functions, and only in the case of the suspension can be cleared.
Platform: | Size: 817152 | Author: 张廷 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字钟的VHDL源程序，可实现整点报时、闹钟的功能，还有常有星期的显示，已调试过-Digital Clock in VHDL source code, enabling the whole point timekeeping, alarm clock function, there are often weeks of shows that have been debug
Platform: | Size: 1339392 | Author: 玉峰 | Hits:

[VHDL-FPGA-Verilog] train

Description: 用 VHDL语言实现闹钟功能，可用于数字钟设计的单元电路，显示电路程序。-Using VHDL language realize alarm function, can be used for the design of digital clock circuit, display circuit procedures.
Platform: | Size: 1024 | Author: 李林 | Hits:

[VHDL-FPGA-Verilog] CLOCK

Description: 可以调整时间和设置闹钟的数字钟(VHDL)-Can adjust the time and set the digital clock alarm clock (VHDL)
Platform: | Size: 906240 | Author: iyoung | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字钟的程序，功能说明如下所示： 1.完成秒／分／时的依次显示并正确计数； 2.秒／分／时各段个位满10正确进位，秒／分能做到满60向前进位； 3.定时闹钟：实现整点报时，通过语音设备来实现具体的报时； 4.时间设置，也就是手动调时功能：当认为时钟不准确时，可以分别对分／时钟进行调整 5.可以选择使用12进制计时或者24进制计时。使用QuartusII6.0编译仿真通过，语言使用的是VHDL，可以方便的移植到其他的平台上面。 -Digital clock procedures, functional description is as follows: 1. Completed sec/min/h and the sequence shows the correct count 2. Sec/min/h in the paragraphs of the correct 10-bit full binary, seconds/minutes to achieve the age of 60 to the forward position 3. regular alarm clock: realize the whole point of time, through the voice equipment to realize specific time 4. time settings, which is manually adjusted when the function: When the clock does not consider accurate, they can respectively sub/clock adjust 5. can choose to use 12 or 24 hexadecimal hexadecimal time time. QuartusII6.0 simulation through the use of compiler, language used is VHDL, can be easily ported to other platforms above.
Platform: | Size: 232448 | Author: 余宾客 | Hits:

[Software Engineering] digitalclockbasedoFPGA

Description: 有时间显示与设置、秒表、闹钟、日期显示与设置功能，用6个数码管显示。 -Has the time display and settings, stopwatch, alarm clock, date display and setting function, using six digital tube display.
Platform: | Size: 211968 | Author: 卓义伟 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 两个按键控制校时的VHDL时钟源码，带定时闹钟和日历功能-Two buttons control the school at the time of VHDL source clock, alarm clock and calendar with timing function
Platform: | Size: 2048 | Author: liu | Hits:

[VHDL-FPGA-Verilog] UP3_RTC_CLOCK

Description: 在UP3开发板上已经验证过的VHDL代码。精确到十分之一秒，具有闹钟，整点报时，时间可重新设置等功能，在LCD1602上显示。绝对推荐，比网上其他类似代码功能要全而且经过验证。最关键的是该代码是直接通过I2C总线来获取UP3开发板上的实时时钟芯片的时间的,当然也可以通过I2C对时钟芯片进行设置.-In the UP3 development board has been verified VHDL code. Accurate to one-tenth of seconds, with the alarm clock, the whole point timekeeping, time and other functions can be re-instated in the LCD1602 display. Absolutely recommended online than other similar features to the entire code and verified. Most crucial point is that the code is directly through the I2C bus to obtain the UP3 development board real time clock chip time, of course, can also I2C clock chip on the set.
Platform: | Size: 1367040 | Author: kehan | Hits:

[VHDL-FPGA-Verilog] clock

Description: 用vhdl设计实现的多功能电子钟，可有日历，闹钟，修改等多种功能-With VHDL Design and Implementation of the multi-functional electronic bell, can have a calendar, alarm clock, to amend a variety of functions such as
Platform: | Size: 1517568 | Author: fana | Hits:

[VHDL-FPGA-Verilog] multifunction_clock

Description: 此为多功能数字电子钟的vhdl代码，有闹钟、时间可调、计时等功能-This is a multi-function digital electronic clock VHDL code, has an alarm clock, time adjustable, timing and other functions
Platform: | Size: 4096 | Author: naturexu | Hits:

[VHDL-FPGA-Verilog] shuzizhong

Description: 设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。实验平台： 1. 一台PC机； 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report
Platform: | Size: 425984 | Author: 盼盼 | Hits:

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[VHDL-FPGA-Verilog] 多功能电子钟

[VHDL-FPGA-Verilog] time_display&alarm_clock

[VHDL-FPGA-Verilog] clock

[Other systems] clock_VHDL

[Software Engineering] clock

[Other] C2

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] train

[VHDL-FPGA-Verilog] CLOCK

[VHDL-FPGA-Verilog] clock

[Software Engineering] digitalclockbasedoFPGA

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] UP3_RTC_CLOCK

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] multifunction_clock

[VHDL-FPGA-Verilog] shuzizhong

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] alarm-clock

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] Alarm_Clock

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