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[VHDL-FPGA-Verilog] 电子钟clock

Description: 用VHDL语言来实现一个电子时钟，可以调时间。小时，分，秒。可以下载到实验箱来运行验证。-use VHDL to achieve an electronic clock, the time can be set aside. Hours, minutes and seconds. Experiments can be downloaded to the box to run test.
Platform: | Size: 353280 | Author: 刘卫 | Hits:

[VHDL-FPGA-Verilog] 8倍频vhdl

Description: 该文件可用vhdl语言实现时钟8倍频，运行环境可在maxplus2和ise的仿真软件上-the document available VHDL Language 8 clock frequency, the operating environment and ideally maxplus2 simulation software
Platform: | Size: 1024 | Author: 罗兵武 | Hits:

[VHDL-FPGA-Verilog] VHDL-Clock

Description: 用VHDL语言写的时钟程序。采用模块化编程。可在EPM7128芯片上下载。编译环境可用Maxplus或Quartus。-write VHDL clock procedures. Modular programming. The EPM7128 chips download. Build environment or Quartus Maxplus available.
Platform: | Size: 4096 | Author: 单单 | Hits:

[Other] VHDL-FPGA-clock

Description: ＦＰＧＡ数字钟的设计，用VHDL语言编程，max+plus仿真，可在实际电路中验证-FPGA design, VHDL programming, max plus simulation, in the actual circuit verification
Platform: | Size: 269312 | Author: 王越 | Hits:

[VHDL-FPGA-Verilog] clock

Description: vhdl经典源代码——时钟设计，入门者必须掌握-vhdl classical source code-- Clock Design, beginners must master
Platform: | Size: 1014784 | Author: jeffery | Hits:

[VHDL-FPGA-Verilog] clock

Description: 用VHDL语言编写的一个闹钟程序，可以整点报时，设置时间，设置闹钟。-VHDL language using an alarm clock to prepare procedures, can be the whole point of time, set time, set an alarm clock.
Platform: | Size: 768000 | Author: zhg | Hits:

[Embeded-SCM Develop] VHDL

Description: VHDL数字钟 数字电子钟 此数字电子钟具有的功能包括： 1. 计时，时、分、秒显示； 2. 十二小时与二十四小时之间的转换； 3. 上下午显示； 4. 对时、分、秒的校时功能；-VHDL digital clock digital clock digital electronic clock with this function include: 1. Time, hours, minutes and seconds display 2. 12 hours and 24 hours between the conversion 3. On the afternoon show 4. hours, minutes and seconds of the school function
Platform: | Size: 3072 | Author: HJGJGHK | Hits:

[Software Engineering] clock

Description: 基于vhdl的数字钟 有闹钟,秒表,时钟,日期等功能 秒表可以开始,暂停,清零, 时钟可以设置时间, 还可以设置日期-VHDL based on the digital clock has an alarm clock, stopwatch, clock, date, stopwatch functions can start, pause, cleared, the clock can be set-up times, you can set the date
Platform: | Size: 3072 | Author: 张廷 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 这是一个实现时分秒的时钟功能的源码，采用vhdl语言编写，已写好led驱动，可直接在数码管上显示-Realize this is an accurate clock function when the source code, the use of VHDL language has been written led drive directly in the digital tube display
Platform: | Size: 246784 | Author: xiaoshuai | Hits:

[VHDL-FPGA-Verilog] clock

Description: vhdl写的电子钟例程，包括多个文件，者的参考。内容简练。作为教学用的。-write VHDL electronic bell routines, including more than documents, the reference. Concise content. Used as the medium of instruction.
Platform: | Size: 4096 | Author: cathy | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字钟的VHDL源程序，可实现整点报时、闹钟的功能，还有常有星期的显示，已调试过-Digital Clock in VHDL source code, enabling the whole point timekeeping, alarm clock function, there are often weeks of shows that have been debug
Platform: | Size: 1339392 | Author: 玉峰 | Hits:

[VHDL-FPGA-Verilog] CLOCK

Description: 可以调整时间和设置闹钟的数字钟(VHDL)-Can adjust the time and set the digital clock alarm clock (VHDL)
Platform: | Size: 906240 | Author: iyoung | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字钟的程序，功能说明如下所示： 1.完成秒／分／时的依次显示并正确计数； 2.秒／分／时各段个位满10正确进位，秒／分能做到满60向前进位； 3.定时闹钟：实现整点报时，通过语音设备来实现具体的报时； 4.时间设置，也就是手动调时功能：当认为时钟不准确时，可以分别对分／时钟进行调整 5.可以选择使用12进制计时或者24进制计时。 使用QuartusII6.0编译仿真通过，语言使用的是VHDL，可以方便的移植到其他的平台上面。 -Digital clock procedures, functional description is as follows: 1. Completed sec/min/h and the sequence shows the correct count 2. Sec/min/h in the paragraphs of the correct 10-bit full binary, seconds/minutes to achieve the age of 60 to the forward position 3. regular alarm clock: realize the whole point of time, through the voice equipment to realize specific time 4. time settings, which is manually adjusted when the function: When the clock does not consider accurate, they can respectively sub/clock adjust 5. can choose to use 12 or 24 hexadecimal hexadecimal time time. QuartusII6.0 simulation through the use of compiler, language used is VHDL, can be easily ported to other platforms above.
Platform: | Size: 232448 | Author: 余宾客 | Hits:

[VHDL-FPGA-Verilog] cpld-clock

Description: VHDL语言编写的时钟显示代码，简短而又易懂，个人觉得很不错-VHDL language code of the clock display, the short and easy-to-understand, personal feel very good
Platform: | Size: 1024 | Author: 王盗大 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 自己编写的一个verilog时钟程序，在xilinx的ISE仿真通过-I have written a Verilog clock procedures, in Xilinx s ISE simulation through
Platform: | Size: 327680 | Author: lg | Hits:

[VHDL-FPGA-Verilog] multifunction_clock

Description: 此为多功能数字电子钟的vhdl代码，有闹钟、时间可调、计时等功能-This is a multi-function digital electronic clock VHDL code, has an alarm clock, time adjustable, timing and other functions
Platform: | Size: 4096 | Author: naturexu | Hits:

[assembly language] clock

Description: 描述了24小时计时的数字钟，同时具有分秒计时的功能-Described a 24-hour digital time clock, at the same time every minute timer function
Platform: | Size: 11264 | Author: 金珊珊 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 基于VHDL的电子时钟设计-VHDL-based design of an electronic clock
Platform: | Size: 241664 | Author: peter | Hits:

[VHDL-FPGA-Verilog] clock

Description: 可以实现时间调节，十二，二十四小时转换，定时，闹钟的时钟-Can be time-conditioning, 12, 24 hours conversion, time, alarm clock
Platform: | Size: 416768 | Author: 王明 | Hits:

[VHDL-FPGA-Verilog] alarm-clock

Description: 基于vhdl的数字闹钟的设计。可实现计时、闹钟、调节时间功能。可以在FPGA上实现。-VHDL-based digital alarm clock design. Can achieve a time, alarm clock, adjust time function. FPGA implementation can be on.
Platform: | Size: 2048 | Author: tony | Hits:
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