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[VHDL-FPGA-Verilog] Ripple_Carry_counter

Description: Ripple Carry Counter. the synchronous version of Ripple Counter. a bit less fasr version the ripple counter but a synchronmous one that will work well on FPGA. wrriten in behavioral VHDL.
Platform: | Size: 20480 | Author: avi | Hits:

[Algorithm] Counter

Description: Squeak Counter .. a nice example for little smalltak
Platform: | Size: 1024 | Author: rapboyx | Hits:

[VHDL-FPGA-Verilog] counter

Description: 用Verilog HDL语言实现FPGA的频率等精度测量。（已经过验证）-Using Verilog HDL language, such as FPGA frequency measurement accuracy. (Has already been verified)
Platform: | Size: 2582528 | Author: double | Hits:

[JSP/Java] counter

Description: java实现的手机版计算器，可供初学者参考-handset counter realization
Platform: | Size: 23552 | Author: 金晓峰 | Hits:

[SCM] temperature

Description: 此设计以单片机STC89C51为核心，由声音传感器采集脉搏信号，经过LM324前置放大电路、滤波电路和比较电路后得到与脉搏相关的脉冲信号，将该脉冲信号作为定时/计数器T1中断信号交由单片机进行脉冲周期的计算，T0做定时器。然后得出每分钟的脉搏搏动次数(即心率)，并将结果1602LCD上显示心率。在对人体脉搏检测时，具有检错排错的功能。若出现误操作（如不小心移动时产生的噪声）造成检测到的心跳次数不正确的结果，所以在程序中检测时间到达第5秒时，先对其进行计算，若结果超出正常范围则自动返回重新检测，直至结果正确，再继续检测5秒，最终由单片机计算出结果。在测量数据超过正常范围(如大于120次／min或小于45次／min)时自动重新开始检测。-Single-chip STC89C51 this design as the core, by the sound pulse sensor signal acquisition, the LM324 preamp circuit, filter circuit and compare the circuit to be associated with the pulse of the pulse signal, the pulse signal as the timer/counter interrupt signal cross-T1 single-chip pulse by calculating the cycle, T0 timer so.And then concludes that the pulse per minute pulse frequency (ie heart rate), and the results show 1602LCD heart rate. Pulse detected in the human body when debugging with the function of error. If misoperation (such as careless move noise) to detect the heartbeat caused by an incorrect number of results, so in the process of testing the time taken to reach the first five seconds, the first of its calculation,If the results exceed the normal range will automatically return to re-testing until the results of the right to continue testing for 5 seconds, the final results calculated by the single chip. In the measurement data over the normal range (for example, m
Platform: | Size: 1024 | Author: 郑雄 | Hits:

[Program doc] counter

Description: Counter 0 to 5MHz by jenda23
Platform: | Size: 2048 | Author: jenda23 | Hits:

[VHDL-FPGA-Verilog] db0358fc-1f16-4f07-9f0f-defb77998bb1

Description: fpga实现简单的计数器功能，用vhdl写的，有一个LED-fpga simple counter function
Platform: | Size: 580608 | Author: zx | Hits:

[Embeded-SCM Develop] c8051f330

Description: 基于C8051F330的正弦波、PWM、计数器、频率测试等功能实现-C8051F330 based on the sine wave, PWM, counter, frequency of testing functions
Platform: | Size: 40960 | Author: linxiand | Hits:

[Software Engineering] counter

Description: source code of drive for counter micro
Platform: | Size: 6144 | Author: azad | Hits:

[VHDL-FPGA-Verilog] counter

Description: 初学者学习modelsim的好例子，基于Verilog的计数器，带测试源码，在quartus2运行。-Modelsim beginners to learn a good example of Verilog based on the counter, with the test source code, running in quartus2.
Platform: | Size: 3906560 | Author: | Hits:

[Special Effects] sel_key

Description: verilog写的自动识别的加减计数器，挺好的，也算有自适应能力-Automatic Identification verilog written addition and subtraction counter, very good, and it has adaptive ability to count
Platform: | Size: 15360 | Author: 山哥 | Hits:

[SCM] counter

Description: 使用51和数码管做的一个计数器，虽然网上很多，但不能满足实际应用，我做的这个已经使用了一段时间，很稳定，你要是想移植到其他程序里，也可以使用（内含仿真图，）-The use of 51 and digital control to do a counter, even though many online, but you can not meet the practical application, I do have to use this for some time, it is stable, if you would like to transplant to other programs, can also be used (including simulation of Figure ,)
Platform: | Size: 44032 | Author: herry_lee | Hits:

[Windows Develop] frequency-meer-8mhz-counter-atmega32

Description: frequency meer 8mhz counter atmega32
Platform: | Size: 46080 | Author: dehghan | Hits:

[VHDL-FPGA-Verilog] up_down_counter

Description: 32 bit up/down counter with count enable based on altera fpga
Platform: | Size: 463872 | Author: abu_faisul | Hits:

[VHDL-FPGA-Verilog] counter

Description: Counter for VHDL Project
Platform: | Size: 1024 | Author: Darek | Hits:

[SCM] COUNTER

Description: 2051单片机控制LED显示计数器功能。-2051 CONTROL THE LED COUNTER
Platform: | Size: 1024 | Author: lina | Hits:

[Software Engineering] counter48

Description: 48 bitt counter for fpga
Platform: | Size: 2048 | Author: rrnair | Hits:

[SCM] C51-counter

Description: 用C51座位CPU的计算器，具备8位数加减乘除功能。P0作为数码管的段控制，P2作为数码管位显示控制，P3控制4x4键盘阵列。-C51 as the CPU, the counter can process 8 bit numbers "+,-,*,/". P0 contro the LED and P2 for which bit,P3 oprate the keyborad
Platform: | Size: 2048 | Author: 梁文梓 | Hits:

[SCM] plj

Description: 这是一个基于51单片机的频率计，本人已经试过。里面还有PROTEUS仿真图-This is a microcontroller based on 51 frequency counter, I have tried. There is also PROTEUS simulation diagram
Platform: | Size: 58368 | Author: 黄化 | Hits:

[Other] counter

Description: 频率计，自动记录信号波形，宽频，四位，自动换挡-Frequency counter, automatic recording signal waveform, broadband, 4, auto-shift
Platform: | Size: 138240 | Author: 那唐 | Hits:
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