Search - digital lock

[VHDL-FPGA-Verilog] 数字锁相环

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
Platform: | Size: 124928 | Author: 于洪彪 | Hits:

[Other] abcdefghijk

Description: 这是一个数字密码锁的VHDL源代码花了很多时间才弄来的-This a digital code lock VHDL source code spent a lot of time obtained
Platform: | Size: 2048 | Author: 星星 | Hits:

[VHDL-FPGA-Verilog] mimasuo

Description: 用VHDL编写的数字密码锁,很实用，喜欢请下载-Prepared using VHDL digital code lock, it is practical, likes to download
Platform: | Size: 2048 | Author: ding | Hits:

[VHDL-FPGA-Verilog] LOCK

Description: 以QuatusⅡ为平台，采用VHDL语言实现数字密码锁的功能，可以仿真实现。-To Quatus Ⅱ as a platform, the use of VHDL language digital code lock function, you can realize simulation.
Platform: | Size: 187392 | Author: cheng sonja | Hits:

[Communication] gfuzzy

Description: 基于模糊逻辑控制的数字锁相环，用于通信系统中的载波恢复。Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.-Based on fuzzy logic control of digital phase-locked loop for the communication system in carrier recovery. Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.
Platform: | Size: 33792 | Author: gogomx | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 基于EDA技术的数字密码锁源程序代码,大学实训用的着-EDA-based Digital code lock source code, used by the University Training
Platform: | Size: 7168 | Author: shark | Hits:

[Other Embeded program] lock

Description: 单片机实现4×4键盘及8位数码管显示构成的电子密码锁，带有keil程序以及protuos的模拟电路。-SCM 4 × 4 keyboard and 8-bit digital tube display constitutes an electronic code lock with keil procedures and protuos of analog circuits.
Platform: | Size: 87040 | Author: 李子超 | Hits:

[VHDL-FPGA-Verilog] ElectronicCodeLock

Description: 设计一个通用电子密码锁，具体功能如下：[1]数码输入 [2]数码清除 [3]密码更改 [4]激活电锁 [5]解除电锁-The design of a universal electronic code lock, the specific features are as follows: [1] digital input [2] Digital Clear [3] Password Change [4] to activate electric lock [5] the lifting of electric locks
Platform: | Size: 1024 | Author: 小夏 | Hits:

[VHDL-FPGA-Verilog] CodeLock

Description: 用于模仿密码锁的工作过程。完成密码锁的核心控制功能。可实现数码输入、清除、退位、设置密码、错误提示、系统报警、解除报警、系统关闭等功能。-Used to imitate the work of the code lock process. Locks achieve the core control functions. Digital input can be achieved, clear, step down, set a password, error message, the system alarm, lift the alarm, turn off the functions of the system.
Platform: | Size: 13312 | Author: 胡婕 | Hits:

[OS Develop] DIGITALLOCK

Description: Verilog code for Digital lock
Platform: | Size: 1024 | Author: nikx | Hits:

[VHDL-FPGA-Verilog] PLL

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-Digital phase-locked loop PLL is the design source code, which, Fi is the input frequency (receive data), Fo (Q5) is a local output frequency. The purpose is to extract data from the input clock signal (Q5), their frequency and data rate in line clock rising edge of lock-in data on rising and falling edge PLL.GDF top-level document
Platform: | Size: 126976 | Author: 许伟 | Hits:

[assembly language] lock

Description: 1、在NMBER INPUT的基础上设计数字密码锁 2、运行初始密码为学号后8位，密码不正确执行4、5功能 3、连续3次密码错误，锁定键盘，发出报警指示 4、输出开锁信号（使用功率开关），LED指示设置修改密码功能，数据存入24C01EEROM -1, in NMBER INPUT design based on digital code lock 2, the initial password for the school run after No. 8, the password is not the correct implementation of 4,5 function 3, for 3 times the wrong password, keyboard lock, the police issued instructions 4, output unlock signal (using the power switch), LED Change Password function instructions, data deposited 24C01EEROM
Platform: | Size: 34816 | Author: 鱼与水 | Hits:

[VHDL-FPGA-Verilog] digital_lock

Description: Verilog code for digital combinational lock //BCAC – Unlock sequence //wrong sequence –alaram goes on and goes off only after pressin another 4 wrong buttons. //once the lock is open ,we can close the lock by pressin any key //From any state pressin AA gets back to reset state.-Verilog code for digital combinational lock //BCAC – Unlock sequence //wrong sequence –alaram goes on and goes off only after pressin another 4 wrong buttons. //once the lock is open ,we can close the lock by pressin any key //From any state pressin AA gets back to reset state.
Platform: | Size: 7168 | Author: deepa | Hits:

[VHDL-FPGA-Verilog] VHDL(LOCK)

Description: 数字密码锁的设计与实现一．实验目的 1. 学习VHDL的综合设计应用 2. 学习数字密码锁的设计二．实验内容设计一个数字密码锁，对其编译，仿真，下载。数字密码锁具体要求如下： 1.系统具有预置的初始密码“00000001”。 2.输入密码与预存密码相同时，开锁成功，显示绿灯，否则开锁失败，显示红灯。 3.具有修改密码功能。修改密码时，先开锁，开锁成功才可以修改。 4.系统同时具有关锁功能。关锁后，显示红灯。 5.密码由拔码开关表示，开锁由按键表示。 6具有一个复位按键。按键后，回到初始状态。 -VHDL Digital Design and Implementation of lock 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning digital code lock design 2. Experimental content Design a digital lock on their compilation, simulation, download. Digital code lock specific requirements are as follows: 1. System has preset the initial password "00000001." 2. Enter the same password with the stored password, unlock successful, a green light, or unlock failed to show a red light. 3. With the change password function. Modify password, the first lock, unlock success can modify. 4. The system also has off lock. Shut up after the red light. 5. The password code from the pull switch that unlock the keys, said. 6 has a reset button. Button, the return to initial state.
Platform: | Size: 18432 | Author: 爱好 | Hits:

[Windows Develop] DIGITAL-LOCK-CODE

Description: DIGITAL LOCK CODE using keypad
Platform: | Size: 2048 | Author: Smita | Hits:

[VHDL-FPGA-Verilog] digital-lock

Description: 电子密码锁功能如下: l、按键接口的设计包括： 1）键盘扫描电路 2）弹跳消除电路 3）键盘译码电路 4）按键存储电路 2、密码锁的控制电路设计包括： 1）按键的数字输入、存储及清除 2）功能按键的功能设计 3）移位寄存器的设计与控制 4）密码清除、变更、存储、激活电锁电路 5）密码核对、解除电锁电路 3、输出七段显示电路的设计包括： 1）数据选择电路 2）BCD对七段显示译码电路 3）七段显示扫描电路密码锁功能说明： 1、数据输入：每按一个数字键，就输入一个数值，并在显示器上的最右方显示出该数值，并将先前已经输入的数据依序左移一个数字位置。 2、数码清除：按下此键可清除前面所有的输入值，清除成为“0000”。 3、密码更改：按下此键时将日前的数字设定成新的密码。 4、激活电锁：按下此键可将密码锁上锁。 5、解除电锁：按下此键会检查输入的密码是否正确，密码正确即开锁。 -Electronic locks l, key interface design Include: 1) The keyboard scanning circuit 2) bounce elimination circuit 3) Keyboard decoding circuit 4) The button memory circuit 2, the lock control circuit design Include: 1) Press the digital input, storage and removal 2) The functional design of function keys 3) Design and Control of the shift register 4) remove the password, change, storage, activate the electric lock circuit 5) The password check, the lifting power lock circuit 3, the output of seven-segment display circuit Include: 1) data selection circuit 2) BCD seven segment display decoder circuit of 3) seven segment display scanning circuit Password Lock Function: 1, the data entry: Each press a number key to enter a value, and in the far right on the display shows the number and order of input data previously left a number of locations. 2, Digital Clear: Press this key to clear all previous input values , clear
Platform: | Size: 130048 | Author: ldong1989 | Hits:

[VHDL-FPGA-Verilog] Digital-lock-design

Description: 1、了解数码锁的工作原理。 2、了解数码锁的实现方法。 3、进一步掌握4×4键盘的扫描的实现过程 -1, to understand the working principle of the digital lock. 2, to understand the implementation of digital locks. 3, to further understand the 44 keypad scanning the implementation process
Platform: | Size: 1846272 | Author: | Hits:

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[VHDL-FPGA-Verilog] 数字锁相环

[Other] abcdefghijk

[VHDL-FPGA-Verilog] mimasuo

[VHDL-FPGA-Verilog] LOCK

[Communication] gfuzzy

[VHDL-FPGA-Verilog] vhdl

[Other Embeded program] lock

[VHDL-FPGA-Verilog] ElectronicCodeLock

[VHDL-FPGA-Verilog] CodeLock

[OS Develop] DIGITALLOCK

[VHDL-FPGA-Verilog] PLL

[assembly language] lock

[VHDL-FPGA-Verilog] digital_lock

[VHDL-FPGA-Verilog] VHDL(LOCK)

[Windows Develop] DIGITAL-LOCK-CODE

[VHDL-FPGA-Verilog] digital-lock

[VHDL-FPGA-Verilog] Digital-lock-design

[VHDL-FPGA-Verilog] digital-lock

[Software Engineering] FPGA-design-digital-lock-in-amplifie

[SCM] Arduino based digital lock

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