Search - fft core

[VHDL-FPGA-Verilog] FFT变换的IP核的源代码 VHDL~

Description: FFT变换的IP核的源代码 VHDL~-FFT IP core of the source code for VHDL ~
Platform: | Size: 31744 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] FFT_CORE

Description: FFT算法的VHDL语言实现可在Modelsim上运行和调试 -FFT algorithm VHDL in the operation and Modelsim Debugging
Platform: | Size: 29696 | Author: 紫蓝 | Hits:

[Mathimatics-Numerical algorithms] 81i_radix2_xfft1024_v3_2

Description: xilinx FFT using ip core project navigator-xilinx ip using FFT core project navigator
Platform: | Size: 1432576 | Author: ningchang | Hits:

[Compress-Decompress algrithms] fft

Description: VHDL语言编写的fft变换的ip核代码对算法感兴趣的可以-VHDL language fft transform algorithm ip core code can be interested in
Platform: | Size: 459776 | Author: liujl | Hits:

[VHDL-FPGA-Verilog] cfft

Description: CFFT是一个数据宽度和点数都可配置的基4 FFT core,用VHDL实现-CFFT is a data width and the base points can be configured 4 FFT core, using VHDL realize
Platform: | Size: 168960 | Author: | Hits:

[VHDL-FPGA-Verilog] 16Point-FFT

Description: 16点FFT VHDL源程序，The xFFT16 fast Fourier transform (FFT) Core computes a 16-point complex FFT. The input data is a vector of 16 complex values represented as 16-bit 2’s complement numbers – 16-bits for each of the real and imaginary component of a datum.-16:00 FFT VHDL source code, The xFFT16 fast Fourier transform (FFT) Core computes a 16-point complex FFT. The input datais a vector of 16 complex values represented as 16-bit 2 s complement numbers- 16-bits foreach of the real and imaginary component of a datum.
Platform: | Size: 1824768 | Author: qiyuan | Hits:

[Other] VHDL_Core_for_1024_Point_Radix_4_FFT_Computation.

Description: This paper shows the development of a 1024-point radix-4 FFT VHDL core for applications in hardware signal processing, targeting low-cost FPGA technologies. The developed core is targeted into a Xilinx庐 Spartan鈩?3 XC3S200 FPGA with the inclusion of a VGA display interface and an external 16-bit data acquisition system for performance evaluation purposes. Several tests were performed in order to verify FFT core functionality, besides the time performance analysis highlights the core advantages over commercially available DSPs and Pentium-based PCs. The core is compared with similar third party IP cores targeting resourceful FPGA technologies. The novelty of this work is to provide a lowcost, resource efficient core for spectrum analysis applications.
Platform: | Size: 456704 | Author: alex | Hits:

[VHDL-FPGA-Verilog] studyFFTcore

Description: 调用FPGA的IP核实现FFT运算，在xilinx的vertex4sx55FPGA的实现-Call FPGA implementation of the IP core FFT computation, in the Xilinx implementation of the vertex4sx55FPGA
Platform: | Size: 1287168 | Author: 徐成发 | Hits:

[VHDL-FPGA-Verilog] fft

Description: 基于FPGA的51核，vhdl，FPGA开发。-FPGA-based 51-core, vhdl, FPGA development.
Platform: | Size: 7714816 | Author: goujinxing | Hits:

[VHDL-FPGA-Verilog] fft_gen

Description: FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results. here is what I do: 1- from core generator I choose fft core and create .vhd & .vho & .xco files. 2- I add the .xco & .vhd files to my project. 3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.-FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results. here is what I do: 1- from core generator I choose fft core and create .vhd & .vho & .xco files. 2- I add the .xco & .vhd files to my project. 3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.
Platform: | Size: 6144 | Author: Jayesh | Hits:

[Other] FFT

Description: IP核！！高速傅立叶变换的VHDL源代码可以综合-IP core! ! High-speed Fourier transform of the VHDL source code can be integrated!!
Platform: | Size: 31744 | Author: 殷桃 | Hits:

[Other] fftsoft

Description: 应用altera的最新fft核做的使用范例，fft核遵循avalon总线。对于想使用altera的IP core的朋友有帮助-Application of nuclear altera do the latest example of the use fft, fft nuclear follow avalon bus. Who want to use the IP core of friends altera help
Platform: | Size: 4036608 | Author: 样样 | Hits:

[VHDL-FPGA-Verilog] cFFT

Description: CFFT is a radix-4 fast Fourier transform (FFT) core with configurable data width and a configurable number of sample points in the FFT. Twiddle factors are implemented using the CORDIC algorithm, causing the gain of the CFFT core to be different from the standard FFT algorithm. This variation in gain is not important for orthogonal frequency division modulation (OFDM) and demodulation. The gain can be corrected, to that of a conventional FFT, by applying a constant multiplying factor.
Platform: | Size: 183296 | Author: Nagendran | Hits:

[VHDL-FPGA-Verilog] rax2

Description: rax2 fft implation the fft in verilog instance and in ise of xilinx it show how to istance fft core and the port used
Platform: | Size: 1024 | Author: LL | Hits:

[SCM] fft

Description: fft程序，最初在单片机c8051f020上实现，“fft.c”是核心程序，很短，程序中x_real[N]是输入序列，输出保存在x_real[N]和x_imag[N]中-fft program, initially implemented on the MCU c8051f020, " fft.c" is the core program, very short, the program x_real [N] is the input sequence, the output stored in x_real [N] and x_imag [N] in
Platform: | Size: 2048 | Author: 樊胜利 | Hits:

[VHDL-FPGA-Verilog] fft

Description: 基于VHDL语言编写的FFT程序，256点，旋转因子存在自己编写的ROM里面，乘法器和数据存储采用的是IP核-FFT-based program written in VHDL, 256 points, there is rotation factor which I have written the ROM, multiplier, and data storage is used in IP core
Platform: | Size: 6144 | Author: 胡佳 | Hits:

[VHDL-FPGA-Verilog] fft_ug

Description: altera的FFT IP核的用户手册，介绍了如何使用ALTERA IP核生成FFT核，如何设置参数并讲述了如何仿真，适用于通信方面的FPGA设计工程师，学生。-altera' s FFT IP core user manual describes how to use the ALTERA IP core generated FFT core, how to set parameters and describes how to simulate, for communications, FPGA design engineers, students.
Platform: | Size: 1035264 | Author: zhangdong | Hits:

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[VHDL-FPGA-Verilog] FFT变换的IP核的源代码 VHDL~

[VHDL-FPGA-Verilog] FFT_CORE

[Mathimatics-Numerical algorithms] 81i_radix2_xfft1024_v3_2

[Compress-Decompress algrithms] fft

[VHDL-FPGA-Verilog] cfft

[VHDL-FPGA-Verilog] 16Point-FFT

[Other] VHDL_Core_for_1024_Point_Radix_4_FFT_Computation.

[VHDL-FPGA-Verilog] studyFFTcore

[VHDL-FPGA-Verilog] fft

[VHDL-FPGA-Verilog] fft_gen

[Other] FFT

[Other] fftsoft

[VHDL-FPGA-Verilog] cFFT

[VHDL-FPGA-Verilog] rax2

[SCM] fft

[VHDL-FPGA-Verilog] fft

[VHDL-FPGA-Verilog] fft_ug

[VHDL-FPGA-Verilog] FFT

[VHDL-FPGA-Verilog] vhdl-fft-core

[Other] AD多通道采集 FFT实验

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