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Description: 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Platform: |
Size: 45110 |
Author: 蔡孟颖 |
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Description: 毕业课题部分程序：
CY7C68013 Bulk IN 68013工作在AUTO IN模式，16位总线 SLAVE FIFO.MASTER是 ADI BF533。
Platform: |
Size: 55443 |
Author: 张衡 |
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Description: 16×4bit的FIFO设计,VHDL语言编的的，能在ISE上仿真出来结果。
Platform: |
Size: 4491 |
Author: 张军 |
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Description: 用16*8 RAM实现一个同步先进先出（FIFO）队列设计。由写使能端控制该数据流的写入FIFO，并由读使能控制FIFO中数据的读出。写入和读出的操作由时钟的上升沿触发。当FIFO的数据满和空的时候分别设置相应的高电平加以指示。
Platform: |
Size: 1302250 |
Author: lavien520@163.com |
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Description: 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Platform: |
Size: 45056 |
Author: 蔡孟颖 |
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Description: 毕业课题部分程序：
CY7C68013 Bulk IN 68013工作在AUTO IN模式，16位总线 SLAVE FIFO.MASTER是 ADI BF533。-Graduated from some of the procedures subject: CY7C68013 Bulk IN 68013 work in the AUTO IN mode, 16-bit bus SLAVE FIFO.MASTER is ADI BF533.
Platform: |
Size: 55296 |
Author: 张衡 |
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Description: 16×4bit的FIFO设计,VHDL语言编的的，能在ISE上仿真出来结果。-16 × 4bit the FIFO design, VHDL language series that can come out in the ISE on the simulation results.
Platform: |
Size: 4096 |
Author: 张军 |
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Description:
1.利用FLEX10KE系列（EPM10K100EQC240-1X）的CLOCKBOOST
（symbol:CLKLOCK）,设计一个2倍频器，再将该倍频器2分频后输出。
对其进行时序仿真。
2.设计一个数据宽度8bit，深度是16的
同步FIFO(读写用同一时钟)，具有EMPTY、FULL输出标志。
要求FIFO的读写时钟频率为20MHz，
将1－16连续写入FIFO，写满后再将其读出来（读空为止）。
仿真上述逻辑的时序，将仿真波形打印出来（与第1题放在同一个PROJECT中）。
3.设计一个数据宽度8bit，深度是16的异步FIFO（读写时钟不相同），
当读写时钟的频率分别为wrclk＝40MHz、rdclk＝20MHz时，仿真其逻辑波形。
-1. FLEX10KE series using (EPM10K100EQC240-1X) of CLOCKBOOST (symbol: CLKLOCK), the design of a 2 frequency multiplier, and then the multiplier 2 hours after the output frequency. Its timing simulation. 2. The design of a data width of 8bit, depth of 16 synchronous FIFO (read and write with the same clock), with EMPTY, FULL output signs. FIFO read and write requests of the clock frequency of 20MHz, the 1-16 consecutive write FIFO, written after the read (read until empty). Simulation of the above-mentioned logical timing, simulation waveforms will print out (with the No. 1 title on the same PROJECT in). 3. To design a data width of 8bit, the depth is 16 asynchronous FIFO (read and write clock is not the same), when read and write clock frequencies were wrclk = 40MHz, rdclk = 20MHz, the simulation waveform of its logic.
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Size: 53248 |
Author: 李侠 |
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Description: VERILOG
Synchronous FIFO. 4 x 16 bit words.-VERILOGSynchronous FIFO. 4 x 16 bit words.
Platform: |
Size: 2048 |
Author: likui |
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Description: a 16 by 4 ram is used for many applications as a basic component such as fifo and stack etc
Platform: |
Size: 1024 |
Author: sri |
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Description: 16*16位的先进先出队列FIFO程序,可作参考-16* 16-bit FIFO queue FIFO procedures, can be used for reference
Platform: |
Size: 1024 |
Author: whywhy |
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Description: 16×4bit的FIFO设计代码，学习代码，请在下载24小时后删除。-16 × 4bit the FIFO design code, learning the code, please delete after 24 hours to download.
Platform: |
Size: 1024 |
Author: yanyinhong |
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Description: libftdi - A library (using libusb) to talk to FTDI s UART/FIFO chips
including the popular bitbang mode.
Main developers:
Intra2net AG <opensource@intra2net.com>-libftdi - A library (using libusb) to talk to FTDI s UART/FIFO chips
including the popular bitbang mode.
Main developers:
Intra2net AG <opensource@intra2net.com>
Platform: |
Size: 427008 |
Author: Changju Lee |
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Description: verilog 实现FIFO存储功能，八位数据宽度，16数据深度。-verilog achieve FIFO memory functions, eight-bit data width, the depth of 16 data.
Platform: |
Size: 60416 |
Author: liaoju |
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Description: 一个同步FIFO，该FIFO深度为16，每个存储单元的宽度为8位，产生FIFO为空、满、半满、溢出标志。-A synchronous FIFO, the FIFO depth of 16, each storage unit width of 8, asked to produce the FIFO is empty, full, half full, the overflow flag.
Platform: |
Size: 1024 |
Author: raul |
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Description: 同步FIFO设计一个同步FIFO，该FIFO深度为16，每个存储单元的宽度为8位，要求产生FIFO为空、满、半满、溢出标志。请采用可综合的代码风格进行编程。-Synchronous FIFO design a synchronous FIFO, the FIFO depth is 16, the width of each memory cell is 8, required to generate the FIFO is empty, full, half full, the overflow flag. Please use the code can be integrated programming style.
Platform: |
Size: 1024 |
Author: 王谦 |
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Description: 同步fifo vhdl语言 16乘以8 能够进行仿真- 16 synchronous fifo vhdl language can be simulated by 8
Platform: |
Size: 18432 |
Author: 浅桑 |
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Description: STC15F2K60S2实现串口FIFO,MODBUS RTU协议,支持03 16指令8继电器,8ADC,8IO采集-STC15F2K60S2 achieve serial FIFO, MODBUS RTU protocol to support 0316 instruction 8 relay, 8ADC, 8IO collection
Platform: |
Size: 223232 |
Author: 方海钰 |
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Description: KEY Scan FIFO for STM32F103
Platform: |
Size: 487424 |
Author: tj_style |
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Description: 用16*8 RAM实现一个同步先进先出（FIFO）队列设计。由写使能端控制该数据流的写入FIFO，并由读使能控制FIFO中数据的读出。写入和读出的操作由时钟的上升沿触发。当FIFO的数据满和空的时候分别设置相应的高电平加以指示(mplementation of a synchronous first in first out (FIFO) queue design with 16*8 RAM. A write FIFO that controls the data stream by writing enable terminals and controls read of data in the FIFO by the read enable. The operation of writing and reading is triggered by the rising edge of the clock. When the data of FIFO is full and empty, set the corresponding high level to indicate)
Platform: |
Size: 264192 |
Author: 渔火
|
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