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[Other resource] Freq_counter

Description: 本代码介绍了使用VHDL开发FPGA的一般流程，最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL，在软件开发平台ISE上完成，可以在较高速时钟频率（100MHz）下正常工作。该设计的频率计能准确的测量频率在1Hz到100MHz之间的信号。使用ModelSim仿真软件对VHDL程序做了仿真，并完成了综合布局布线，最终下载到芯片Spartan-II上取得良好测试效果。-the code on the FPGA using VHDL development of the general process, finally adopted a FPGA-based digital frequency method. The design using VHDL hardware description language, the software development platform ISE completed, the higher speed clock frequency (100MHz) under normal work. The design of the frequency meter can be accurately measured in a frequency of 100MHz between Hz signal. Use ModelSim VHDL simulation software to do the simulation process, and completed a comprehensive layout cabling, downloaded to the final chip Spartan-II made good on the test results.
Platform: | Size: 514889 | Author: 许的开 | Hits:

[VHDL-FPGA-Verilog] Freq_counter

Description: 本代码介绍了使用VHDL开发FPGA的一般流程，最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL，在软件开发平台ISE上完成，可以在较高速时钟频率（100MHz）下正常工作。该设计的频率计能准确的测量频率在1Hz到100MHz之间的信号。使用ModelSim仿真软件对VHDL程序做了仿真，并完成了综合布局布线，最终下载到芯片Spartan-II上取得良好测试效果。-the code on the FPGA using VHDL development of the general process, finally adopted a FPGA-based digital frequency method. The design using VHDL hardware description language, the software development platform ISE completed, the higher speed clock frequency (100MHz) under normal work. The design of the frequency meter can be accurately measured in a frequency of 100MHz between Hz signal. Use ModelSim VHDL simulation software to do the simulation process, and completed a comprehensive layout cabling, downloaded to the final chip Spartan-II made good on the test results.
Platform: | Size: 515072 | Author: 许的开 | Hits:

[VHDL-FPGA-Verilog] modelsim

Description: 基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256点的fft -Memory based on the base 4 by the frequency of fft taken the VHDL description of the continuous data stream can be carried out 256 point fft
Platform: | Size: 22528 | Author: 庞志勇 | Hits:

[Embeded-SCM Develop] digital_system_CAD_lab_direction

Description: 数字系统CAD 开发平台实验部分共有6 个实验，内容覆盖了ISE 的设计使用、片内逻 辑分析仪ChipScope 的使用、设计仿真工具Modelsim 的使用、以及嵌入式系统设计工具EDK的使用等内容。在每个实验的说明中分别介绍它们的使用。 包括： 实验一、7 段数码管显示简单的时钟 实验二、设计串口与计算机通信 实验三、A/D 采样模块设计 实验四、使用DAC7634 设计频率发生器 实验五、频率发生器的设计与仿真 实验六、应用嵌入式系统设计基本的串口收发程序 实验七、视频解码和图像显示-CAD development platform for digital system experimental part of a total of six experiments, the content covers the use of ISE design, on-chip logic analyzer ChipScope use, the design of the use of ModelSim simulation tools, as well as embedded system design tools such as content use EDK. In each experiment, respectively, a note on their use. Include: the experimental one, paragraph 7 of digital display clock simple experiment II, the design of serial communication and computer experiment III, A/D sampling experiment four modular design, the use of design DAC7634 experimental five-frequency generator, frequency generator design and simulation Experimental six, application of embedded system design basic experimental procedures seven serial transceiver and video decoding and image display
Platform: | Size: 1178624 | Author: abcoabco | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设 计，包括偶数分频、非 50％占空比和 50％占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使 用的电路，并在 ModelSim 上进行验证。 -This article describes the use of examples in the FPGA/CPLD prescaler to use VHDL to design, including the even-numbered sub-frequency, non-50 duty cycle and 50 duty cycle of the odd-numbered sub-frequency, semi-integer (N+ 0.5) sub-frequency, fractional-N, as well as scores of sub-band frequency points. All can realize through the Synplify Pro or FPGA manufacturers integrated synthesizer to form a circuit can be used and verified in the ModelSim on.
Platform: | Size: 322560 | Author: 黄鹏曾 | Hits:

[VHDL-FPGA-Verilog] twice_clk

Description: 对输入时钟进行2倍频 已在modelsim中通过仿真 建议进行后仿 应用上来看 是可以使用的-the function of the module is frequency multiplication，and the module had been test and verified by modelsim,so the products can be employed with 100 ease by each consumer.think you!!!!
Platform: | Size: 5120 | Author: 王伟臣 | Hits:

[VHDL-FPGA-Verilog] fpga_balance_project

Description: 此文件是2009年全国大学生电子设计大赛数字幅频均衡功率放大器的数字部分工程文件，包括modelsim的仿真部分。-This file is the 2009 National Undergraduate Electronic Design Contest figures the number of amplitude-frequency balanced power amplifier part of the project documents, including the modelsim simulation part.
Platform: | Size: 14126080 | Author: 肖康 | Hits:

[VHDL-FPGA-Verilog] fenpin

Description: 在modelsim环境下实现的计数器分频，希望和大家分享-Realized in the environment in modelsim frequency counter, would like to share
Platform: | Size: 27648 | Author: 叶亮 | Hits:

[VHDL-FPGA-Verilog] VHDL_fre_div

Description: 使用VHDL进行分频器设计 本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设 计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过Synplify Pro或FPGA生产厂商的综合器进行综合，形成可使 用的电路，并在ModelSim上进行验证。-For crossover design using VHDL This paper describes the use of examples in the FPGA/CPLD design using VHDL for divider Design, including even frequency, duty cycle and 50 of non-50 duty cycle of the odd frequency, half-integer (N+0.5) frequency, fractional, fractional and integral crossover frequency. Can all achieve Synplify Pro FPGA by or integrated device manufacturers an integrated, enables the formation of With the circuit, and on the ModelSim verification.
Platform: | Size: 322560 | Author: guoguo | Hits:

[VHDL-FPGA-Verilog] dds

Description: 在quartus下的DDS设计，Verilog语言，可以产生正弦波、三角波、方波等，频率可调。-Under the DDS in quartus design, Verilog language, you can produce sine wave, triangle wave, square wave, frequency adjustable.
Platform: | Size: 2632704 | Author: 米多 | Hits:

[VHDL-FPGA-Verilog] dds

Description: DDS数字式频率合成器 利用VERILOG实现，有modelsim仿真图-DDS digital frequency synthesizer using VERILOG realization, modelsim simulation diagram
Platform: | Size: 382976 | Author: | Hits:

[SCM] adfmreceiver

Description: The design of the All Digital FM Receiver circuit in this project uses Phase Locked Loop (PLL) as the main core. The task of the PLL is to maintain coherence between the input (modulated) signal frequency,iωand the respective output frequency,oωvia phase comparison. This self-correcting ability of the system also allows the PLL to track the frequency changes of the input signal once it is locked. Frequency modulated input signal is assumed as a series of numerical values (digital signal) via 8-bit of analog to digital conversion (ADC) circuit. The FM Receiver gets the 8 bit signal every clock cycle and outputs the demodulated signal. The All Digital FM Receiver circuit is designed using VHDL, then simulated and synthesized using ModelSim SE 6 simulator and Xilinx ISE 6.3i, respectively. FPGA implementation also provided, here we use Virtex2 device.
Platform: | Size: 658432 | Author: vijay | Hits:

[VHDL-FPGA-Verilog] verilog1

Description: 用verilog语言编写的6分频分频计数器。分频后用来控制蜂鸣器响，也可以修改代码做成更高分频的计数器。压缩包内也包含此分频器的modelsim仿真文件-Verilog language with 6 frequency divider counter. Frequency and used to control the buzzer sound, you can modify the code to make a higher frequency counter. Compressed package also contains this file divider modelsim simulation
Platform: | Size: 143360 | Author: 广子 | Hits:

[VHDL-FPGA-Verilog] EP3C8020111219125810_ROM_OK5

Description: 采用DSP builder v9.1实现正交两路单频输出，已经在EP3C80上面跑通，经实际验证是正确的。此例程非常简洁明了，可以作为DSP builder的入门示例。里面已经包含了生成好的modelsim仿真示例和仿真结果。-Achieved using DSP builder v9.1 orthogonal two single-frequency output, has been run through the EP3C80 above, are proven to be correct. This routine is very simple and clear, as DSP builder of the Getting Started Sample. Which has been included to generate good modelsim simulation Examples and simulation results.
Platform: | Size: 13917184 | Author: 刘洋 | Hits:

[VHDL-FPGA-Verilog] fenpin

Description: FPGA分频通用程序，使用时修改一个参数即可，使用modelsim开发环境-Frequency FPGA procedures, when used to modify a parameter, use the Modelsim development environment
Platform: | Size: 50176 | Author: 刘石海 | Hits:

[VHDL-FPGA-Verilog] sinx

Description: 完整的正弦波频率产生，详细的源程序以及完整仿真，对学习vhdl及eda很有帮助，在modelsim中仿真-Complete sine wave frequency generator
Platform: | Size: 404480 | Author: okitaaoi | Hits:

[VHDL-FPGA-Verilog] fre

Description: verilog hdl 开发的频率计，运行环境 DE2-115开发板，内有modelsim仿真用的testbench。RTL级代码-verilog hdl developed frequency meter, operating environment, the DE2-115 development board, modelsim simulation of the testbench. RTL-level code
Platform: | Size: 4446208 | Author: 甜甜 | Hits:

[VHDL-FPGA-Verilog] traffic_Light

Description: 模拟十字路口交通灯的VHDL程序，附有用与配合ModelSim的仿真程序。 内容：交通灯设计 （1）A，B方向各有红，黄，绿灯，初始态全为红灯，之后东西方向通车，绿灯灭后，黄灯闪烁，各路口通车时间为30秒，由两个七段数码管计数，当显示时间小于3秒的时候通车方向黄灯闪烁 （2）系统时钟1KHz，黄灯闪烁时钟要求为2Hz，七段码管的时间显示为1Hz脉冲，即1秒递减一次，在显示时间小于3秒时，通车方向的黄灯以2Hz的频率闪烁，系统中加入外部复位信号。 （3）用ModelSim做仿真 -VHDL program simulate the crossroads of traffic lights, accompanied with the ModelSim simulation program. : Traffic light design (1) A, B, the direction of each red, yellow, green, and the initial state of all the red, the east-west direction after the opening of the green off, flashing yellow light, the intersection open to traffic for 30 seconds by two seven segment LED count, (2) the opening of the direction of the yellow light flashes when the display time is less than 3 seconds when the system clock 1KHz, flashing yellow light clock requirements for 2Hz, seven segment tubes 1Hz pulse, that is a seconds, decreasing the display time of less than 3 seconds, the opening direction of the yellow light is flashing, the system by adding an external reset signal frequency of 2Hz. (3) with ModelSim simulation
Platform: | Size: 1024 | Author: 陈若耿 | Hits:

[VHDL-FPGA-Verilog] Digital-frequency-meter

Description: 数字频率计 ，Quartus 10.0+modelsim 6.5SE联仿真报告形式-Digital frequency meter,simulation with Quartus 10.0+ modelsim 6.5SE ，reports。
Platform: | Size: 277504 | Author: dailanfeng | Hits:

[VHDL-FPGA-Verilog] 1

Description: 简单的组合逻辑设计，简单分频时序逻辑电路的设计，利用条件语句实现计数分频时序电路(Simple combinatorial logic design, design of simple frequency division sequential logic circuit and Realization of counting frequency division timing circuit by conditional statement)
Platform: | Size: 1024 | Author: 随风sf | Hits:
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