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[Software Engineering] eee DL : 0: 并行AVS实时编解码器设计与实现介绍了一种并行AVS实时编码器的设计，它包括音视频数据输入、音视频编码、传输流系统复用器、输出和控制部分，其中重点介绍了视频编码器和传输流系统复用器的设计和实现。实验结果证明，实现标清AVS实时编码器是可行的。-Parallel real-time codec AVS Design and Implementation of AVS introduce a parallel real-time encoder design, which includes audio and video data entry, audio and video encoding, transport stream multiplexer system, the output and control parts, which focuses on video encoding and Transport Stream Multiplexer System Design and Implementation. Experimental results show that AVS realize SDTV real-time encoder is feasible.
Update : 2025-02-17 Size : 301kb Publisher : sss
[Windows Develop] ```` DL : 0: Multiplexer 16-to-4 using Selected Signal Assignment Statement
Update : 2025-02-17 Size : 2kb Publisher : 左
[Software Engineering] SOPC_MPEG2_trainsformer DL : 0: 论文题目：基于SOPC的MPEG2传输流复用器设计-Thesis topic: Based on SOPC the MPEG2 transport stream multiplexer design
Update : 2025-02-17 Size : 28kb Publisher : 张贺
[Graph program] mp4creator-win32-1.6.1e-pre DL : 0: A MPEG4 Multiplexer/Demultiplexer to create IETF standards-conform streams with additional Quicktime support for chapters and anamorphic resizing
Update : 2025-02-17 Size : 233kb Publisher : yanyuan
[Other Embeded program] 4to1MUX DL : 0: Verilog code for 4 t0 1 multiplexer
Update : 2025-02-17 Size : 2kb Publisher : wajahat
[VHDL-FPGA-Verilog] Multiplexer DL : 0: 这是一个用vhdl硬件描述语言实现的乘法器而不是多路选择器-this is an implimentation of an multiplier rather than multiplexer.
Update : 2025-02-17 Size : 142kb Publisher : maxpayne
[VHDL-FPGA-Verilog] 16-1MUX DL : 0: 16 down to 1 Multiplexer in Vhdl
Update : 2025-02-17 Size : 64kb Publisher : Abdullah
[Windows Develop] multiplexer DL : 0: implementation of multiplexer circuit-implementation of multiplexer circuit..
Update : 2025-02-17 Size : 154kb Publisher : zeeshan
[VHDL-FPGA-Verilog] multiplexer DL : 0: multiplexer xilinx FPGA
Update : 2025-02-17 Size : 303kb Publisher : kkkkkk
[VHDL-FPGA-Verilog] multiplexer DL : 0: A program for a simple multiplexer using modelsimSE6.3
Update : 2025-02-17 Size : 8kb Publisher : Subhaiit
[VHDL-FPGA-Verilog] multiplexer DL : 0: 几种常用乘法器的Verilog、VHDL代码-Several common multiplier Verilog, VHDL code
Update : 2025-02-17 Size : 261kb Publisher : kk
[VHDL-FPGA-Verilog] multiplexersemultiplexer DL : 0: this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural
Update : 2025-02-17 Size : 89kb Publisher : jatab
[Other] multiplexer DL : 0: this is a multiplexer
Update : 2025-02-17 Size : 4kb Publisher : eminem
[Windows Develop] Multiplexer DL : 0: 這是一個4位元的多工器，是由一個2位元的多工器所構成-This is a 4-bit multiplexer is determined by a 2-bit multiplexer posed by
Update : 2025-02-17 Size : 81kb Publisher : tw
[Software Engineering] AD7992 DL : 0: The AD7992 is a 12-bit, low power, successive approximation ADC with an I2C-compatible interface. The part operates from a single 2.7 V to 5.5 V power supply and features a 2 μs conver-sion time. The part contains a 2-channel multiplexer and track-and-hold amplifier
Update : 2025-02-17 Size : 719kb Publisher : d
[Com Port] multiplexer DL : 0: 一个关于gsm协议的 multiplexer protocol 的研究笔记希望大家可以从中受益-An agreement on the multiplexer protocol gsm research notes hope that we can benefit from
Update : 2025-02-17 Size : 209kb Publisher : lidengtao
[VHDL-FPGA-Verilog] Multiplexer DL : 0: Source code of multiplexer on VHDL. The compilation is done in Quartus II for Cyclone II.
Update : 2025-02-17 Size : 448kb Publisher : Dave
[VHDL-FPGA-Verilog] 5-multiplexer DL : 0: five multiplexer, verilog, altera de2 board~
Update : 2025-02-17 Size : 2kb Publisher : KYchocz
[VHDL-FPGA-Verilog] Multiplexer-Description DL : 0: 通过应用QUARTUSII开发软件对二选一多路选择器进行设计并运行结果-Software development through the application of QUARTUSII choose one of two multiplexer design and operation results
Update : 2025-02-17 Size : 10kb Publisher : renee
[VHDL-FPGA-Verilog] Multiplexer-Description2 DL : 1: 通过应用QUARTUSII开发软件对四选一多路选择器进行设计，并给出运行结果-Software development through the application of QUARTUSII choose one of four multiplexer design, and operating results are given
Update : 2025-02-17 Size : 14kb Publisher : renee

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