Search - phase accumulator

[Other] dds

Description: FPGA实现直接数字信号源.一个相位累加器的设计-FPGA realization of direct digital signal source. A phase accumulator design
Platform: | Size: 5120 | Author: 马彩青 | Hits:

[Other] b

Description: A high-speed variable phase accumulator for an ADPLL architecture
Platform: | Size: 287744 | Author: bc | Hits:

[VHDL-FPGA-Verilog] sum_ten

Description: 十位累加器,EDA,FPGA,DDS信号发生器的相位累加器,可用.-Accumulator 10, EDA, FPGA, DDS signal generator of the phase accumulator can be used.
Platform: | Size: 3072 | Author: seasonroad | Hits:

Description: 相位累加器，即DDS频率合成器的MATALB实现，采用M文件编写的S函数-Phase accumulator, that is, the DDS frequency synthesizer MATALB realized, the use of M' s S function documentation
Platform: | Size: 1024 | Author: 曹刚 | Hits:

[VHDL-FPGA-Verilog] dds_easy

Description: 直接频率合成DDS模块的ise工程，可以直接下载，在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波，也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位，可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram，为节省储存空间仅需要储存1/4周期的数据。根据需要，可以重新修改数据，改变波形。-DDS direct frequency synthesizer module ，ise project, can be directly downloaded through the Spartan3/Spartan3E and tested successfully. The DDS module can generate two-channel sine wave of different frequency, or produce the same frequency arbitrary waveform phase difference of the phase shift. There is a 32-bit accumulator to generate 12 bit phase-precision 12-bit quantization precision of the sine wave. Cases the design of a Block Ram, in order to save storage space need to store only 1/4 cycle of data. Necessary, can modify data, change the waveform.
Platform: | Size: 471040 | Author: 郭先生 | Hits:

[Windows Develop] Desktop

Description: DDS数字频率合成DDS由相位累加器、正弦查找表、D／A转换器和低通滤波器组成 -DDS DDS DDS from the phase accumulator, sine look-up tables, D/A converter and low-pass filter composed of
Platform: | Size: 1024 | Author: chenxiaofeng | Hits:

[Embeded Linux] 83390078DDS

Description: DDS的工作原理是以数控振荡器的方式产生频率、相位可控制的正弦波。电路一般包括基准时钟、频率累加器、相位累加器、幅度/相位转换电路、D/A转换器和低通滤波器（LPF）。频率累加器对输入信号进行累加运算，产生频率控制数据X（frequency data或相位步进量）。相位累加器由N位全加器和N位累加寄存器级联而成，对代表频率的2进制码进行累加运算，是典型的反馈电路，产生累加结果Y。幅度/相位转换电路实质上是一个波形寄存器，以供查表使用。读出的数据送入D/A转换器和低通滤波器。-DDS works the way we are digitally controlled oscillator frequency, phase controlled sine wave. Circuits generally include reference clock, frequency accumulator, phase accumulator, amplitude/phase converter circuit, D/A converter and low-pass filter (LPF). The frequency accumulator to accumulate the input signal operation to produce the frequency control data X (frequency data or phase stepping volume). From the N-bit phase accumulator and the N-bit full adder cascade accumulation register is made on behalf of the frequency of the two binary codes accumulation operation, is a typical feedback circuit, resulting in cumulative results of Y. Amplitude/phase converter circuit is essentially a waveform register for look-up table to use. Read out the data into the D/A converter and low pass filter.
Platform: | Size: 44032 | Author: 394177191 | Hits:

[Software Engineering] DDS1

Description: 直接数字频率合成器（Direct Digital synthesizer）是从相位概念出发直接合成所需波形的一种频率合成技术。一个直接数字频率合成器由相位累加器、加法器、波形存储ROM、D/A转换器和低通滤波器（LPF）构成-Direct digital frequency synthesizer (Direct Digital synthesizer) is the concept of direct synthesis from the requirements phase of a waveform synthesizer technology. A direct digital frequency synthesizer by the phase accumulator, adder, waveform storage ROM, D/A converter and low pass filter (LPF) constitute
Platform: | Size: 261120 | Author: wufeng | Hits:

[VHDL-FPGA-Verilog] xiangweileijiaqi

Description: 相位累加器，是数字频率合成器的重要组成部分。这是verilog代码。-Phase accumulator, digital frequency synthesizer is an important part. This is the verilog code.
Platform: | Size: 2048 | Author: yanzhengkuaile | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 本设计中应用硬件描述语言Verilog HDL描述相位累加器，相位调制器，正弦波、方波、三角波、心电波形四个独立的波形存储器，并描述频率控制、相位控字、幅度控制单元及波形切换等相关的功能单元。-Application of the design described in Verilog HDL hardware description language phase accumulator, phase modulator, sine, square, triangle wave, the four independent ECG waveform memory, and describe the frequency control, phase control word, control unit and the waveform amplitude switching and other related functional units.
Platform: | Size: 4096 | Author: kelly | Hits:

[VHDL-FPGA-Verilog] vhdl2

Description: vhdl语言正弦信号发生器设计，传统的用分立元件或通用数字电路元件设计电子线路的方法设计周期长,花费大, 可移植性差。本文以正弦波发生器为例,利用EDA 技术设计电路,侧重叙述了用VHDL 来完成直接数字合成器(DDS) 的设计,DDS 由相位累加器和正弦ROM 查找表两个功能块组成,其中ROM查找表由兆功能模块LPM-ROM来实现。-The traditional use of discrete components or general purpose digital circuit design method of electronic circuit design cycle is long, expensive, poor portability. In this paper, sine wave generator, for example, circuit design using EDA technology, focusing on the use of VHDL description to complete the direct digital synthesizer (DDS) design, DDS ROM from the phase accumulator and sine lookup table composed of two functional blocks, including ROM lookup table by the LPM-ROM modules trillion to implement.
Platform: | Size: 94208 | Author: 枫蓝 | Hits:

[VHDL-FPGA-Verilog] SG_FPGA

Description: 2006年电子设计竞赛二等奖，多功能函数、信号发生器核心器件FPGA内部的原理图，主要模块用VHDL代码描述，包括PLL、相位累加器、波形算法和正弦波查找表，可实现0.005Hz~20MHz的多波形信号产生，频率步进值0.005，输出接100MSPS速率的DAC--AD9762-Electronic Design Competition 2006, second prize, multi-function signal generator within the core of the device schematic FPGA, VHDL code with the description of the main modules, including the PLL, phase accumulator, sine lookup table algorithm and the waveform can be realized 0.005Hz ~ 20MHz multi-waveform signal generator, the frequency step value of 0.005, then the output rate of 100MSPS DAC- AD9762
Platform: | Size: 1099776 | Author: zlz | Hits:

[Software Engineering] jia

Description: 摘要:介绍了利用直接数字合成技术产生频率扫描信号的新方法。利用计数器和相位累加器实现对波形存储器寻址, 从而产生频率扫描信号序列。该序列通过数-模转换器和低通滤波器后, 产生出频率扫描信号。被合成的频率扫描信号的起始频率、终止频率和扫描时间可根据需要随意设定,并且可以实现对三者的精确控制。-Abstract: The use of direct digital synthesis techniques to create a new method of frequency sweep signal. The use of counters and phase accumulator to achieve the waveform memory addressing, resulting in a frequency sweep signal sequence. The sequence through the number- analog converter and low pass filter, to produce a frequency sweep signal. Was synthesized frequency sweep signal the start frequency, stop frequency and sweep time can be arbitrarily set according to need, and can achieve precise control of the three.
Platform: | Size: 148480 | Author: 贾琼 | Hits:

[VHDL-FPGA-Verilog] acc32bit

Description: 本设计为32位数字相位累加器，门级描述的Verilog代码。其中，acc32bit.v为顶层文件，full_add1.v为一位全加器的门级描述模块，flop.v为触发器的门级描述模块。-The design for the 32-bit digital phase accumulator, gate-level description of the Verilog code. Which, acc32bit.v as top-level file, full_add1.v as a full adder gate-level description module, flop.v to trigger the gate-level description of the module.
Platform: | Size: 755712 | Author: 吴亮 | Hits:

[GPS develop] Code_NCO.zip

Description: 码数控振荡器相位累加器的位数N为32,利用verilog HDL语言在Quartus II 9.1中具体实现了载波和码NCO的设计。,The code numerically controlled oscillator phase accumulator bits N 32 verilog HDL language in the concrete realization of the design of the carrier and code NCO Quartus II 9.1.
Platform: | Size: 1024 | Author: cc | Hits:

[VHDL-FPGA-Verilog] VHDL-DDS

Description: 基于FPGA的DDS信号源设计，32位相位累加器，产生可调频率-FPGA-based DDS signal source design, 32-bit phase accumulator to generate tunable frequency
Platform: | Size: 1024 | Author: 春雷 | Hits:

[Editor] Code(6)

Description: As the figure above illustrates, a phase accumulator compares the sample clock and desired frequency to increment a phase register. Again, the fundamental idea is that we can generate signals with precise frequencies by generating an appropriate sample based on the phase of that frequency at any point in time. In addition, by representing our waveform with 214 (16,384) points, we are able to represent exactly 16,384 phase increments with our lookup table.
Platform: | Size: 9216 | Author: maddy | Hits:

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