Description: 流密码算法,可用于文件加密和实时通信
,设计者是著名的密码学家Rivest.该算法效率远高于一般分组密码,并且很适合用于随机数生成-Stream cipher algorithm, can be used for file encryption and real-time communication, the designer is well-known cryptographer Rivest. The algorithm efficiency is much higher than the general block cipher, and is suitable for random number generator Platform: |
Size: 2048 |
Author:che wang |
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Description: verilog编写随机数产生源程序，在硬件电路设计中应用广泛。本程序是在LFSR and a CASR 基础上实现的-random number generator to prepare Verilog source code, in the hardware circuit design applications. This procedure is in the LFSR and a CASR based on the Platform: |
Size: 94208 |
Author:Alex |
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Description: 写的一个用lcd1602的随机数发生器，用的语言为Verilog，工具是Quartus II软件。-Write a random number generator with lcd1602, the language used for the Verilog, Quartus II software tool. Platform: |
Size: 2398208 |
Author:无名 |
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Description: Verilog code for a pseudo random number generator using linear shift registers. Implemented on Basys2 with Xilinx. Project report also is included. Platform: |
Size: 1177600 |
Author:sndn_shr |
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Description: this a verilog code of true random number generator using butterfly puf-this is a verilog code of true random number generator using butterfly puf Platform: |
Size: 4096 |
Author:tahmoures |
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Description: 基于vivado Verilog的伪随机数发生器，采用LFSR算法，并对其进行了升级，使用反馈级联的思想，从最大周期为2^n提升为原来的3-5倍(Based on vivado Verilog pseudo random number generator, using LFSR algorithm, and upgrade it, using the idea of feedback cascade, from the maximum cycle of 2^n to 3-5 times the original) Platform: |
Size: 1889280 |
Author:9901tzh
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Description: 本人用verilog编写的随机数生成文件，经测试可用。(I am prepared to use verilog random number generator, the test is available.) Platform: |
Size: 2880512 |
Author:chenpeiweiweiwei |
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Search - random number generator verilog