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[VHDL-FPGA-Verilog] VHDL CPU部件

Description: 包括一个简单的ALU和一些寄存器、ROM的设计。有一些以TXT文件格式存在，用的时候只要改一下格式即可。
Platform: | Size: 155537 | Author: terminatorsong@gmail.com | Hits:

[Crack Hack] rom_des

Description: DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。-VHDL and VERILOG sourcecode and TESTBENCH of DES encrypting algorithm
Platform: | Size: 30720 | Author: | Hits:

[VHDL-FPGA-Verilog] datarom

Description: 该源码为几个正弦ROM,已经编译并通过,可以直接下载,不需要,内部含有正弦ROM表,还有ROM的宏模块-the source for several sine ROM, has been compiled and passed, can be directly downloaded, not internal ROM containing sine table, the Acer ROM module
Platform: | Size: 243712 | Author: 刘恒辉 | Hits:

[VHDL-FPGA-Verilog] VHDL语言100例详解

Description: VHDL语言100例详解。详细讲解了用VHDL语言进行数字电路和数字系统设计的知识。用100个实例，不仅进行基础的门电路设计，而且还有较为复杂的数字系统设计。这些实例可以直接被调用。-VHDL Elaborates on 100 cases. Detailed account of VHDL for digital circuits and digital systems design knowledge. With 100 examples, not only for infrastructure gate design, but also more complex digital system design. These examples can be called.
Platform: | Size: 6633472 | Author: 穆群生 | Hits:

[VHDL-FPGA-Verilog] blockram

Description: 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
Platform: | Size: 21504 | Author: 孙强 | Hits:

[VHDL-FPGA-Verilog] jop_rom

Description: JOP的RAM VHDL源码，经典的经典，不易找到的好东东，-JOP of RAM VHDL source code, classic classics, difficult to find a good price.
Platform: | Size: 4096 | Author: 黄肖超 | Hits:

[Communication-Mobile] GetRomData

Description: 生成4种方式的DDS输出的读表程序的VHDL源代码程序。-four ways generation of DDS output of the meter reading procedures VHDL source code procedures.
Platform: | Size: 176128 | Author: zhao | Hits:

[VHDL-FPGA-Verilog] ram

Description: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Platform: | Size: 2048 | Author: nick | Hits:

[Other] rom2

Description: vhdl rom 程序，标准的rom程序，很简单-vhdl rom procedures rom standard procedures, is very simple
Platform: | Size: 1024 | Author: gcy | Hits:

[Embeded-SCM Develop] CPLD234

Description: 文档中给出了使用VHDL编写的频率的精确测量方法的代码,同时还有cPLD与e2rom等的接口代码-Document given the frequency of the use of VHDL to prepare precise measurement method of the code, along with e2rom CPLD interface code, etc.
Platform: | Size: 223232 | Author: qibinchuan | Hits:

[VHDL-FPGA-Verilog] i2c

Description: SAA7114 和 FPGA/CPLD之间通讯的程序，本人觉得比较好，而且里面还添加了，ROM，用来存取IIC的常数和读来的数据。-SAA7114 and FPGA/CPLD communication between the procedures, I feel better, but it also added, ROM, used to access the IIC to the constant and time data.
Platform: | Size: 8192 | Author: 张亚伟 | Hits:

[VHDL-FPGA-Verilog] rom

Description: 一个 16×8bit 的ROM程序包括程序的初始化。-A 16 × 8bit the ROM initialization procedures, including procedures.
Platform: | Size: 3072 | Author: h13978699183 | Hits:

[VHDL-FPGA-Verilog] rom

Description: 基于vhdl的rom的描述,经过确定测试通过.-Based on the VHDL description of the rom, after determining the test.
Platform: | Size: 1024 | Author: stone | Hits:

[VHDL-FPGA-Verilog] rom

Description: 我用VHDL写的正弦，用FPGA内部ROM，有仿真testbench,在quartus里可以运行。在板子里已经验证-I used to write VHDL sinusoidal, using FPGA internal ROM, has simulation testbench, you can run in Quartus. Yard has already been verified in the plates
Platform: | Size: 651264 | Author: jimmy | Hits:

[VHDL-FPGA-Verilog] VHDL-ROM4

Description: 基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), waveform generator control module and latch module 2. Waveform data storage module (ROM) custom data width of 8 , address width of 6, can store 64 points sinusoidal waveform data, waveform data are obtained using MATLAB. 3. To 50MHz clock as input.
Platform: | Size: 98304 | Author: 宫逢源 | Hits:

[VHDL-FPGA-Verilog] rom

Description: 只读存储器VHDL代码，可运行实现，已用quartusII6.0验证-Read-only memory VHDL code can be run to achieve has been used to verify quartusII6.0
Platform: | Size: 1024 | Author: 干璐 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 《数字信号处理的FPGA实现》（第二版）光盘VHDL代码-" The FPGA digital signal processing to achieve" (second edition) CD-ROM VHDL code
Platform: | Size: 251904 | Author: 王昊 | Hits:

[SCM] rom

Description: Rom的读取的Verilog代码，自己编写的，大家参考参考啊-Rom read the Verilog code, I have written, your information ah
Platform: | Size: 1024 | Author: keke | Hits:

[VHDL-FPGA-Verilog] rom

Description: 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个ROM存储器。-The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a ROM memory.
Platform: | Size: 179200 | Author: Daisy | Hits:

[VHDL-FPGA-Verilog] VHDL(sin)

Description: 基于ROM的正弦波发生器的设计 一．实验目的 1. 学习VHDL的综合设计应用 2. 学习基于ROM的正弦波发生器的设计 二．实验内容 设计基于ROM的正弦波发生器，对其编译，仿真。 具体要求： 1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based sine wave generator design 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning ROM-based sine wave generator design 2. Experimental content ROM-based sine wave generator design, its compilation, simulation. Specific requirements: 1. Sine wave generator by the data storage module (ROM), waveform generator control module and latch modules Two. Waveform data storage module (ROM) custom data width is 8, the address width of 6, can store 64-point sine wave data, wave data obtained using MATLAB. 3. The 50MHz input clock.
Platform: | Size: 17408 | Author: 爱好 | Hits:
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