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[Embeded-SCM Develop] verilog实例 [43项]

Description: 嵌入式可编程器件CPLD的典型实例 压缩包，共计43个源码文件。 使用ALTERA的 Muxplus 软件即可编辑仿真 相关软件可在教育网ftp下载[天网查询，有很多站点提供]-Embedded Programmable CPLD in a typical example of compressed, for a total of 43 source document. Altera Muxplus use the software can edit simulation software available from the Education Network ftp download [days Web inquiries, many sites provide]
Platform: | Size: 181248 | Author: 吴旭辉 | Hits:

[Other Embeded program] 发一个基于ModelSim仿真的Verilog源代码包

Description: 发一个基于ModelSim仿真的Verilog源代码包-made a ModelSim simulation based on the Verilog source code
Platform: | Size: 74752 | Author: 阿乐 | Hits:

[VHDL-FPGA-Verilog] 结合XILINXCPLD RS232通信(verilog)

Description: 结合XILINXCPLD所做的模拟RS232通信verilog源程序-XILINXCPLD combine the simulation RS232 communication Verilog source
Platform: | Size: 121856 | Author: 于飞 | Hits:

[Other Embeded program] CAN协议控制器的Verilog实现

Description: 基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。-FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.
Platform: | Size: 38912 | Author: wl | Hits:

[Other Embeded program] yunsuan-verilog

Description: 运算器的实现，即实验指导书中的实验一，文件中包含有原代码及端口设置（可变），用vrilog HDL编程，Xilinx ISE 6仿真，并在实际电路中得到实现．-operations for the realization of the experimental guidance of a book. document contains the original code and port settings (variable), with vrilog HDL programming, Xilinx ISE 6 simulation, and the actual circuit realization.
Platform: | Size: 1600512 | Author: 王越 | Hits:

[Other Embeded program] trafficLight-verilog

Description: 交通灯状态机的实现，用verilog HDL编程，Xilinx ISE 6仿真，在实际电路中得到验证．-traffic lights to achieve the state machine, with verilog HDL programming, Xilinx ISE 6 simulation, the actual circuit have been tested.
Platform: | Size: 1532928 | Author: 王越 | Hits:

[VHDL-FPGA-Verilog] 1_061026140305

Description: 基于FPGA的I2C总线模拟，采用verilog HDL语言编写。- Based on the FPGA I2C main line simulation, uses verilog the HDL language compilation.-FPGA-based I2C bus simulation, using verilog HDL language.- Based on the FPGA I2C main line simulation, verilog uses the HDL language compilation.
Platform: | Size: 204800 | Author: | Hits:

[VHDL-FPGA-Verilog] SPI_Code(Verilog)

Description: SPI总线硬件描述语言Verilog下的实现，含主模式和从模式的实现，经过仿真验证，可作为一个单独的模块使用-SPI bus under the Verilog hardware description language to achieve with the main mode and slave mode realization, through simulation, can be used as a separate module uses
Platform: | Size: 5120 | Author: 高兵 | Hits:

[VHDL-FPGA-Verilog] 64

Description: 64位乘法器，超前进位的，大家看看，通过仿真的，verilog的-64-bit multiplier, bit-ahead, let us look at the adoption of simulation, verilog of
Platform: | Size: 37888 | Author: | Hits:

[VHDL-FPGA-Verilog] 8051-Verilog

Description: 使用CPLD仿真8051核,内有源程序和说明,来之不易-CPLD simulation using 8051 nuclear, which has source code and description, the hard-won
Platform: | Size: 90112 | Author: 梁志洪 | Hits:

[Graph Drawing] CadenceSimulationCourse

Description: Cadence Verilog Language and Simulation
Platform: | Size: 1182720 | Author: yuanxiaonan | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: Verilog教程，讲述Verilog在cpld/fpga中从设计到仿真全过程。-Verilog tutorial, Verilog described in cpld/fpga simulation from the design to the entire process.
Platform: | Size: 2479104 | Author: pangyugang | Hits:

[VHDL-FPGA-Verilog] Verilog(piano)

Description: 用VERILOG语言编写的电子琴程序.用GW48教学实验箱仿真的-Using Verilog language organ procedures. GW48 teaching experiment with simulation boxes
Platform: | Size: 5120 | Author: 阿洪 | Hits:

[SCM] Verilog(clock)

Description: 用VERILOG语言编写的电子钟程序.是用GW48教学实验箱仿真-Verilog language using an electronic bell procedures. GW48 is teaching me the experimental simulation
Platform: | Size: 7168 | Author: 阿洪 | Hits:

[VHDL-FPGA-Verilog] Verilog--shiyanbaogao

Description: 有实验结果,用MOSIN6编写的,是Verilog HDL语言实现的. 练习三 利用条件语句实现计数分频时序电路 实验目的： 1. 掌握条件语句在简单时序模块设计中的使用； 2. 学习在Verilog模块中应用计数器； 3. 学习测试模块的编写、综合和不同层次的仿真。 练习四 阻塞赋值与非阻塞赋值的区别 实验目的： 1． 通过实验，掌握阻塞赋值与非阻塞赋值的概念和区别； 2． 了解阻塞赋值与非阻塞赋值的不同使用场合； 3． 学习测试模块的编写、综合和不同层次的仿真。 -The experimental results are used to prepare MOSIN6 is achieved Verilog HDL language. Practice the use of conditional statements to achieve the three sub-frequency timing circuit count experimental purposes: 1. Have conditional statements in the simple timing of the use of modular design 2. Learning modules in the Verilog Application of counter 3. to learn the preparation of the test module, integrated and different levels of simulation. Practicing the four blocking assignment with the distinction between non-blocking assignment experimental purposes: 1. Through experiments, hands blocking assignment with the concept of non-blocking assignment and distinction 2. Understanding of blocking and nonblocking assignment assignment using different occasions 3. Test the preparation of learning modules, integrated and different levels of simulation.
Platform: | Size: 15360 | Author: 盼盼 | Hits:

[VHDL-FPGA-Verilog] NcVerilog_tutorial

Description: nc verilog 的使用说明和实例，对于实用nc来进行仿真进行了详细说明。-nc verilog instructions and examples for the utility to carry out simulation nc described in detail.
Platform: | Size: 591872 | Author: 李林 | Hits:

[VHDL-FPGA-Verilog] verilog-a

Description: verilogA的教材，详细的介绍了语言的用法，主要是用于模拟电路系统建模和仿真。-verilogA materials, detail the usage of the language was mainly used to simulate the circuit system modeling and simulation.
Platform: | Size: 1020928 | Author: 赵晓迪 | Hits:

[VHDL-FPGA-Verilog] Simulation-and-FPGA-Implementation-of-DigitalDBPSK

Description: 文章介绍了系统的硬件电路原理与具体实现方法，其中主要包括载波恢 复电路，PN 码捕获电路和跟踪电路，并针对Xilinx 公司FPGA 的特点，对各电 路的实现进行优化设计，在不影响系统稳定性和精度的前提下，减少硬件资源 消耗，提高硬件利用率。设计利用Verilog 硬件描述语言完成，通过后仿真验证 电路正确性，并给出综合结果。-This paper introduces the system' s hardware circuit principle and the specific implementation methods, which mainly include the carrier recovery circuit, PN code acquisition circuit and track circuits, and FPGA for Xilinx company characteristics, the implementation of the circuit to optimize the design, without affecting the system stability and precision under the premise of reduced hardware resource consumption, improve hardware utilization. Designed using Verilog Hardware Description Language finish, after the passage of the correctness of circuit simulation, and give General results.
Platform: | Size: 1007616 | Author: mayuan | Hits:

[Other Embeded program] I2C19861208888

Description: i2c总线模拟，verilog hdl编写的总线模拟控制程序-i2c bus simulation, verilog hdl prepared bus analog control procedures
Platform: | Size: 11264 | Author: 韩永高 | Hits:

[VHDL-FPGA-Verilog] SDRAM-verilog

Description: SDRAM读写控制的实现与Modelsim仿真-verilog-SDRAM read and write control to achieve with the Modelsim simulation-verilog
Platform: | Size: 2196480 | Author: sjdbjs | Hits:
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