Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - sobel FPGA

Search list

[Other resource] sobel

Description: 这是本人自己编写的可用于256*256大小的图像进行sobel边缘检测的vhd文件，可在QuartusII或MaxplisII下综合和仿真，并在FPGA上测试过。可以进行修改支持其他大小图像的sobel边缘检测，同时还可以实现其它的图像模块化处理算法，例如高斯滤波，平滑等。-this is my own preparation for the 256 * 256 size of the image segmentation Edge Detection vhd document in the next QuartusII or MaxplisII integrated and simulation, and the FPGA tested. Can be adapted to support other size image segmentation edge detection, It can also achieve other modular image processing algorithms, such as Gaussian filtering, smoothing and so on.
Platform: | Size: 3135 | Author: 刘洋 | Hits:

[VC/MFC] 图像边缘检测Sobel算法的FPGA仿真与实现

Description:
Platform: | Size: 230035 | Author: persever2009@126.com | Hits:

[VHDL-FPGA-Verilog] sobel

Description: 这是本人自己编写的可用于256*256大小的图像进行sobel边缘检测的vhd文件，可在QuartusII或MaxplisII下综合和仿真，并在FPGA上测试过。可以进行修改支持其他大小图像的sobel边缘检测，同时还可以实现其它的图像模块化处理算法，例如高斯滤波，平滑等。-this is my own preparation for the 256* 256 size of the image segmentation Edge Detection vhd document in the next QuartusII or MaxplisII integrated and simulation, and the FPGA tested. Can be adapted to support other size image segmentation edge detection, It can also achieve other modular image processing algorithms, such as Gaussian filtering, smoothing and so on.
Platform: | Size: 3072 | Author: 刘洋 | Hits:

[VHDL-FPGA-Verilog] Sobel

Description: 这是一个用VHDL实现SOBEL算子进行图像边缘算法的实现-This is a realization by VHDL Sobel edge operator algorithm
Platform: | Size: 328704 | Author: citydremer | Hits:

[VHDL-FPGA-Verilog] sobel

Description: SOBEL FILTER IN VHDL
Platform: | Size: 1024 | Author: Randa | Hits:

[Software Engineering] sobel_filter

Description: implementation of SOBEL filter using FPGA board RC200 in handle-c
Platform: | Size: 4096 | Author: nishu | Hits:

[VHDL-FPGA-Verilog] sobel

Description: verilog sobel FPGA edge detection-Adopted verilog language realizes sobel edge detection in image processing algorithm
Platform: | Size: 10240 | Author: wkd | Hits:

[VHDL-FPGA-Verilog] DE2_CCD_sobel

Description: verilog编写的适用于fpga的3x3模板sobel滤波-verilog fpga prepared for the 3x3 template sobel filter
Platform: | Size: 5596160 | Author: 彭青艳 | Hits:

[VHDL-FPGA-Verilog] Grayscale-Conversion-IP

Description: Sobel Edge Detection IP for FPGA using LABVIEW
Platform: | Size: 26624 | Author: refaat | Hits:

[Windows Develop] tsobbellh

Description: 这是我本人自己开发的可用于256*256大小的图像进行sobel边缘检测的vhd文件，可在QuartusII或MaxplisII下综合与与仿真，并在FPGA上测试过。能进行修改支持其他大小图像的sobeel边缘检测，同时还能实现其它的图像模块化处理算法，例如高斯滤波，平滑等。 -This is my own development vhd file, can be used for 256* 256 size image sobel edge detection under QuartusII or MaxplisII synthesis and with simulation, and tested on FPGA. Can be modified to support other sobeel size image edge detection, while still achieving other image the modular processing algorithms, such as Gaussian filtering and smoothing.
Platform: | Size: 3072 | Author: 兴奋 | Hits:

[VHDL-FPGA-Verilog] sobel2

Description: 新的sobel算子的FPGA实现。使用verilog语言，并调试通过~-The sobel operator new FPGA implementation. Verilog language, and debugging through to
Platform: | Size: 356352 | Author: abrams | Hits:

[VHDL-FPGA-Verilog] VHDLproject-by-Qian-Yu

Description: 创建一个实时的视频处理器采用了FPGA技术的系统设计与VHDL。在这个项目中，我们实现滑动窗口滤波器，Sobel算子，一系列传感器和数字显示器VGA模块。-create a real-time video processor using FPGA technology in the course System Design with VHDL. In the project we implement modules for sliding window, sobel lter, a range sensor and a number displayer for VGA.
Platform: | Size: 2294784 | Author: Li Chen | Hits:

[Graph program] sobel

Description: 在FPGA中，采用verilog HDL语言实现图像处理算法sobel，仿真实验通过-In the FPGA using verilog HDL language image processing algorithms sobel, simulation experiment
Platform: | Size: 6255616 | Author: zhouhui | Hits:

[Software Engineering] sobel

Description: 这是一个基于sobel算子的FPGA实现的解决方案-Implementation of FPGA based on Sobel operator
Platform: | Size: 272384 | Author: 杨云山 | Hits:

[Special Effects] sobel

Description: 基于FPGA的sobel滤波。使用vivado 2014.2实现的YUV图像的sobel滤波。-Sobel filter based on FPGA. YUV image Sobel filtering using vivado to achieve the 2014.2.
Platform: | Size: 20752384 | Author: 张威 | Hits:

[VHDL-FPGA-Verilog] soble

Description: 基于FPGA的Sobel边缘检测算法的实现与仿真。此程序提供算法的verliog实现。(Implementation and Simulation of Sobel edge detection algorithm based on FPGA. This program provides the verliog implementation of the algorithm.)
Platform: | Size: 5868544 | Author: 我是陌陌同学 | Hits:

[VHDL-FPGA-Verilog] DE2_70_D5M_LTM_sobel

Description: SOBEL TO DETECT IMAGE EDGE
Platform: | Size: 8623104 | Author: chun354 | Hits:

[VHDL-FPGA-Verilog] ece5760-final-cwf38-mao65-as889

Description: BALL GAME + EDGE DETECTION FOR FPGA
Platform: | Size: 14389248 | Author: chun354 | Hits:

[VHDL-FPGA-Verilog] sobel

Description: 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)
Platform: | Size: 10222592 | Author: 丶大娱乐家 | Hits:

[VHDL-FPGA-Verilog] CNN-FPGA-master

Description: 用FPGA实现CNN算法，实现CNN加速(Realization of CNN Algorithms with FPGA)
Platform: | Size: 11264 | Author: 明月心447 | Hits:
« 12 »

CodeBus www.codebus.net