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[Other resource] ADC_16bit

Description: 用verilog硬件描述语言编写的16位数模转换器的源代码，可以综合-with verilog hardware description language of 16 Digital to Analog source code can be integrated
Platform: | Size: 1671 | Author: awp | Hits:

[VHDL-FPGA-Verilog] ADC_16bit

Description: 用verilog硬件描述语言编写的16位数模转换器的源代码，可以综合-with verilog hardware description language of 16 Digital to Analog source code can be integrated
Platform: | Size: 1024 | Author: awp | Hits:

[Software Engineering] FPGA_GPS_C_A

Description: 本文：采用了FPGA方法来模拟高动态(Global Position System GPS)信号源中的C／A码产生器。C／A码在GPS中实现分址、卫星信号粗捕和精码(P码)引导捕获起着重要的作用，通过硬件描述语言VERILOG在ISE中实现电路生成，采用MODELSIM、SYNPLIFY工具分别进行仿真和综合。-This article: FPGA method used to simulate the high dynamic (Global Position System GPS) signal source of the C/A code generator. C/A code in GPS to achieve sub-sites, the satellite signal capture coarse and fine code (P code) lead capture plays an important role, through hardware description language Verilog in ISE to achieve circuit to generate, using MODELSIM, SYNPLIFY simulation tools were and integrated.
Platform: | Size: 163840 | Author: xiaozhu | Hits:

[VHDL-FPGA-Verilog] ethernet__verilog

Description: fpga模拟以太网物理层的源代码，用verilog硬件描述语言开发。-FPGA simulation of the Ethernet physical layer of the source code, using Verilog hardware description language development.
Platform: | Size: 330752 | Author: 王贤 | Hits:

[SCM] AT89C2051

Description: 提出了一种能防止多次试探密码的基于单片机的密码锁设计和实现方案。首先给出了用 户提出的10条总体要求和功能，然后比较详细地介绍了实现该要求的硬件和软件的设计过程，其中包 括单片机型号的选择、硬件设计、软件流程图、单片机存储单元的分配、汇编语言源程序及详细注释 等内容，并且给出了完整的硬件电路图、软件流程图和源程序。-A test on many occasions to prevent the password locks based on single-chip design and implementation of the program. First of all, users are given 10 overall requirements and functions, and then a more detailed description of the achievement of the required hardware and software design process, including the single-chip models, hardware design, software flow chart, Microcontroller the allocation of memory cells, assembly language source code and detailed notes and other content, and gives a complete circuit of the hardware, software flowcharts and source code.
Platform: | Size: 109568 | Author: 罗志坚 | Hits:

[VHDL-FPGA-Verilog] 100Examples

Description: 该源码为用VHDL（硬件描述语言）编写的100个实例的源代码，是学习VHDL的绝好资源。软件环境为maxplus10.2及以上版本或Quartus2。-The source for the use of VHDL (Hardware Description Language) preparation of the 100 examples of the source code, is an excellent resource to learn VHDL. Software environment for maxplus10.2 and above or Quartus2.
Platform: | Size: 209920 | Author: gung66 | Hits:

[VHDL-FPGA-Verilog] ata.tar

Description: 使用verilog和VHDL两种硬件描述语言实现了一个ATA硬盘控制器，包括源代码、测试仿真文件和说明文档-The use of two types of Verilog and VHDL hardware description language to achieve an ATA hard drive controller, including source code, testing, simulation files and documentation
Platform: | Size: 835584 | Author: qinlei | Hits:

[Other Embeded program] ADC0809AD_example

Description: ADC0809A/D转换器基本知识，电路原理图，硬件连线说明，完整的汇编源程序和C语言源程序，都一并放在word文件里面了-ADC0809A/D converter basic knowledge of circuit schematics, hardware description to connect a complete compilation of source code and C language source code, are placed together inside a word document
Platform: | Size: 45056 | Author: 李 | Hits:

[TCP/IP stack] cisc8bitCPU

Description: 一个用硬件描述语言编写的cisc类型8位总线长度cpu实例的源代码-A hardware description language using the CISC type 8-bit bus the length of the source code examples cpu
Platform: | Size: 1091584 | Author: 李建刚 | Hits:

[assembly language] MyGiftPiano

Description: 对这个程序的源代码做了详细的说明。因此它可以做为学习windows消息体制的范例，当然也可以做为32位汇编语言学习的参考资料。(不能作为16位汇编的发音程序的范例,因为我是直接调用的声卡API接口函数,从而隐藏了用直接控制硬件(比如定时器,扬声器)的方法.-Of the source code of this procedure a detailed description. Learning so it can be used as an example of windows message system, of course, can also be employed as the compilation of 32 language learning reference. (Can not be used as compilation of 16 examples of the pronunciation of the procedure, because I am a direct call to the sound card interface API function, and thus hidden by the direct control of hardware (such as timers, speakers) method.
Platform: | Size: 78848 | Author: jason | Hits:

[Windows Develop] example_AHDL

Description: 硬件描述语言AHDL设计编程源程序，包括各种不同用途的代码-AHDL hardware description language design programming source code, including a variety of different uses of the code
Platform: | Size: 494592 | Author: sky | Hits:

[VHDL-FPGA-Verilog] USB

Description: USB的VHDL实现源码（使用VHDL硬件描述语言，通过Altera QuartusII 开发）-USB to achieve the VHDL source code (using VHDL hardware description language, through the development of Altera QuartusII)
Platform: | Size: 50176 | Author: 刘磊 | Hits:

[VHDL-FPGA-Verilog] simpleFIFO

Description: FIFO的VHDL程序,硬件描述语言源码-FIFO process of VHDL hardware description language source code
Platform: | Size: 137216 | Author: 陳皇仁 | Hits:

[VHDL-FPGA-Verilog] EDAVHDL

Description: VHDL硬件描述语言 MAX+PLUSⅡ介绍 CPLD数字发展实验系统简介以及十个数字电路和数字系统实验的源代码和介绍-VHDL hardware description language introduced the MAX+ PLUS Ⅱ Introduction CPLD digital development of experimental systems, as well as 10 digital circuits and digital systems, the source code and introducing experimental
Platform: | Size: 674816 | Author: bryan | Hits:

[Software Engineering] vhdl-TAXI

Description: 随着EDA技术的发展及大规模可编程逻辑器件CPLD／FPGA的出现，电子系统的设计技术和工具发生了巨大的变化，通过EDA技术对CPLD／FPGA编程开发产品，不仅成本低、周期短、可靠性高，而且可随时在系统中修改其逻辑功能。本文利用VHDL语言设计出租车计费系统，使其实现汽车启动、停止、暂停时计费以及预置等功能，通过设置计数电路进行路费及路程的计数，通过设计数据转换电路将路费及路程的十进制数分离成四位十进制数表示，通过设计快速扫描电路显示车费及路费，突出了其作为硬件描述语言的良好的可读性的优点。通过MAX+PLUSⅡ软件编写、调试和优化源程序，下载到特定芯片（MAX系列的EPM 7128SLC8415）后，即可应用于实际的出租车计费系统中。-ith the development of EDA technologies and large-scale programmable logic device CPLD/FPGA emergence of electronic systems design techniques and tools has undergone tremendous changes, through the EDA technology CPLD/FPGA programming product development, not only low-cost, short lead time, high reliability, but also may at any time in the system to modify its logic function. In this paper, VHDL language design taxi billing system to achieve the car to start, stop, pause, time billing and preset functions, by setting the tolls and the distance counting circuit count, through the design of data conversion circuits and the journey will be toll separated into four decimal decimal number, said a quick scan through the design of the circuit shows fares and tolls, highlighting its position as a hardware description language, the advantages of good readability. Through the MAX+ PLUS Ⅱ software development, debugging and optimizing the source code, download to a specific chip (MAX series of EP
Platform: | Size: 269312 | Author: stella | Hits:

[VHDL-FPGA-Verilog] FPGA_SDRAM

Description: FPGA对SDRAM的控制操作源码,用VERILOG硬件描述语言编写,包含的文件一共有:hostcont.v,inc.h,pinouts.ucf,sdram.v,top.v,tst_inc.h-Control of operation of the SDRAM FPGA source code, using VERILOG hardware description language, the file contains a total of: hostcont.v, inc.h, pinouts.ucf, sdram.v, top.v, tst_inc.h
Platform: | Size: 21504 | Author: 陈维 | Hits:

[VHDL-FPGA-Verilog] HDL_lecture_notes_verilog_gatech

Description: Verilog 语言 GaTech大学讲义 ，介绍了verilog基本语法以及基础案例，包含源程序，适合本科硬件描述语言学习参考-Gatech univ lectures of Verilog Language , introduced the verilog basic grammar and basic case, including source code, hardware description language for undergraduate study reference
Platform: | Size: 647168 | Author: hxt | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: EDA技术以EDA软件工具为开发环境，以可编程逻辑器件为实验载体，实现源代码编程和仿真功能。VHDL作为一种标准化的硬件描述语言用于描述数字系统的结构、行为、功能和接口。本设计提出了一种基于VHDL语言的编码器和译码器的实现方法。编码器与译码器是计算机电路中基本的器件，本课程设计采用EDA技术设计编码和译码器。编码器由8线-3线优先编码器作为实例代表，译码器则包含3线-8线译码器和2线-4线译码器两个实例模块组成。课程设计采用硬件描述语言VHDL把电路按模块化方式进行设计，然后进行编程、时序仿真和分析等。课程设计结构简单，使用方便，具有一定的应用价值。 -EDA technology take the EDA software as tools for the development of the environment,programmable logic devices in experimental carrier,the realiztion of the source code programming and simulation. The VHDL as a standardized hardware description language used to describe the struction of digital systems,behavior,function and interface. The paper proposes a method for encoder and decoder based on the VHDL language.Encoder and decoder is a basic computer circuit devices.This Curriculum design by EDA design encoder and decoder.Encoders from 8- 3 priority encoder for example,and decoder includes 3- 8 decoder and the 2- 4 examples of the two decoder modules.And then to program, the timing simulation and analysis.Curriculum design, simple structure, easy to use and has a value.
Platform: | Size: 797696 | Author: pear | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: 此为秒表计数器的硬件描述语言源程序，有清零键和暂停键。该例子比较简单，适合初学者。有分频、十进制、六进制、秒表共四部分组成-This is the stopwatch counter hardware description language source code , a clear key and the Pause button . The example is simple , suitable for beginners . Took part in the frequency , decimal , hex , a total of four components stopwatch
Platform: | Size: 185344 | Author: jacob | Hits:

[VHDL-FPGA-Verilog] Source

Description: This power point file consist of a lot of different vhdl code for component with source code VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.-This power point file consist of a lot of different vhdl code for component with source code VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.
Platform: | Size: 918528 | Author: pouya | Hits:
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