Search - stop_watch

[Other resource] stop_watch

Description: 采用Quartus2编写的电子秒表电路实现计时、暂停等功能
Platform: | Size: 349373 | Author: gz208 | Hits:

[VHDL-FPGA-Verilog] stop_watch

Description: 采用Quartus2编写的电子秒表电路实现计时、暂停等功能-Quartus2 prepared using electronic stopwatch timer circuit, suspension and other functions
Platform: | Size: 349184 | Author: gz208 | Hits:

Description: (1) 精度应大于1／100 s 计时器能显示1／100 s的时间，故提供给计时器内部定时的时钟脉冲频率应大于100 Hz，可选1 kHz。 (2) 计时器的最长计时时间为1 h在一般的短时计时应用中，1 h是足够了。为此需要一个6位的显示器，显示的最长时间为59分59.99秒。 (3) 设置复位和启／停开关复位开关用来使计时器清零，并作好计时准备。启／停开关的使用方法应与传统的机械式计时器相同，即按一下启／停开关，启动计时器开始计时，再按一启／停开关计时终止。复位开关可以在任何情况下使用，即使在计时过程中，只要一按复位开关，计时进程应立刻终止，并对计时器清零。 -err
Platform: | Size: 5120 | Author: 曾伟 | Hits:

[VHDL-FPGA-Verilog] DE2

Description: 使用 DE2板制作的多功能数字钟，含有选择功能，秒表，电子表，闹钟，用7-segment LED液晶显示，可以通过LCD看当时状态附有仿真波形--Clk_Div,- Mode_Select,-Watch,-stop_watch,-Lcd_Module,-Total_Out source code，Simulation waveform
Platform: | Size: 3694592 | Author: 赵香君 | Hits:

[Other] stop_watch

Description: 使用状态机实现的秒表，另外包含计数器功能-The use of state machine to achieve the stopwatch
Platform: | Size: 5120 | Author: yemintao | Hits:

[VHDL-FPGA-Verilog] stop_watch

Description: 实现跑表功能精确度为0.01秒。（使用ACEX1K系列EP1K30TC144-3芯片）-Stopwatch function to achieve an accuracy of 0.01 seconds. (Using ACEX1K series EP1K30TC144-3 chip)
Platform: | Size: 189440 | Author: Haifengqingfu | Hits:

[assembly language] Stop_Watch

Description: （键控秒表）-stop watch
Platform: | Size: 14336 | Author: 难得明白 | Hits:

[VHDL-FPGA-Verilog] stop_watch

Description: This a running stop watch implemented on spartan 2-This is a running stop watch implemented on spartan 2
Platform: | Size: 435200 | Author: illi | Hits:

[VHDL-FPGA-Verilog] stop_watch_1kHz

Description: stop_watch vhdl code
Platform: | Size: 1314816 | Author: urbanmyth | Hits:

[VHDL-FPGA-Verilog] TestBench

Description: TestBench for stop_watch in VHDL
Platform: | Size: 4096 | Author: mmm | Hits:

[File Format] stop_watch

Description: visual basic for stop_watch
Platform: | Size: 8192 | Author: sh | Hits:

[Other Embeded program] stop_watch

Description: this stop watch project written by win avr -this is stop watch project written by win avr
Platform: | Size: 23552 | Author: Mohammad | Hits:

[VHDL-FPGA-Verilog] stop_watch

Description: stop_watch编程，当stop输入为一时程序停止计数，并输出从上一次输入为一的时钟频数-stop_watch programming procedures for the moment when the stop input to stop counting, and the output from the last input clock frequency for a
Platform: | Size: 110592 | Author: 武娇娇 | Hits:

[VHDL-FPGA-Verilog] stop_watch

Description: stopwatch source it is maded by maxplus2
Platform: | Size: 5120 | Author: daesuk | Hits:

[VHDL-FPGA-Verilog] stop_watch

Description: 秒表设计,设计一个秒表计时器，具有全局清零信号和计数使能信号。-Stopwatch design, design a stopwatch timer, has a global reset signal and the count enable signal.
Platform: | Size: 1024 | Author: 朱珈娴 | Hits:

[Windows Develop] STOP_WATCH

Description: 这个代码显示了使窗体、模块和如何使用命令按钮、图片、组合框、定时器等而开始学习VB。这段代码还显示了一些先进的概念就像运行应用程序在后台(系统盘)和如何让你的形式掌握的所有正在运行的应用程序。-This code displays the forms, modules, and how to use the command buttons, images, combo boxes, timers, etc. and start learning VB. This code also shows some advanced concepts like running applications in the background (system tray) and how to get your form held all running applications.
Platform: | Size: 10240 | Author: 南煎丸子 | Hits:

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[Other resource] stop_watch

[VHDL-FPGA-Verilog] stop_watch

[Windows Develop] stop_watch

[VHDL-FPGA-Verilog] DE2

[Other] stop_watch

[VHDL-FPGA-Verilog] stop_watch

[assembly language] Stop_Watch

[VHDL-FPGA-Verilog] stop_watch

[VHDL-FPGA-Verilog] stop_watch_1kHz

[VHDL-FPGA-Verilog] TestBench

[File Format] stop_watch

[Other Embeded program] stop_watch

[VHDL-FPGA-Verilog] stop_watch

[VHDL-FPGA-Verilog] stop_watch

[VHDL-FPGA-Verilog] stop_watch

[Windows Develop] STOP_WATCH

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