Description: 使用Altera芯片实现对4个SAA7111A视频A/D芯片的采集控制，将图像数据存入同步FIFO-AL422B-use Altera chip to 4 SAA7111A Video A/D chip to control the collection, image data are stored in synchronous FIFO- AL422B Platform: |
Size: 1024 |
Author:古韦剑 |
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Description: verilog HDL原码
一种简单的同步FIFO原码，可以被综合-verilog HDL original code a simple synchronous FIFO original code, which can be integrated Platform: |
Size: 1024 |
Author:zxz |
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Description: 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench Platform: |
Size: 2048 |
Author:彭帅 |
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Description: 此文件为同步FIFO的实现源码，同步FIFO可用于硬件中两种总线或器件的缓冲，以保证功能的实现。-This document is the realization of source synchronous FIFO, Synchronous FIFO can be used for two types of hardware or device bus buffer to ensure the realization of function. Platform: |
Size: 2048 |
Author:小明 |
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Description:
1.利用FLEX10KE系列（EPM10K100EQC240-1X）的CLOCKBOOST
（symbol:CLKLOCK）,设计一个2倍频器，再将该倍频器2分频后输出。
对其进行时序仿真。
2.设计一个数据宽度8bit，深度是16的
同步FIFO(读写用同一时钟)，具有EMPTY、FULL输出标志。
要求FIFO的读写时钟频率为20MHz，
将1－16连续写入FIFO，写满后再将其读出来（读空为止）。
仿真上述逻辑的时序，将仿真波形打印出来（与第1题放在同一个PROJECT中）。
3.设计一个数据宽度8bit，深度是16的异步FIFO（读写时钟不相同），
当读写时钟的频率分别为wrclk＝40MHz、rdclk＝20MHz时，仿真其逻辑波形。
-1. FLEX10KE series using (EPM10K100EQC240-1X) of CLOCKBOOST (symbol: CLKLOCK), the design of a 2 frequency multiplier, and then the multiplier 2 hours after the output frequency. Its timing simulation. 2. The design of a data width of 8bit, depth of 16 synchronous FIFO (read and write with the same clock), with EMPTY, FULL output signs. FIFO read and write requests of the clock frequency of 20MHz, the 1-16 consecutive write FIFO, written after the read (read until empty). Simulation of the above-mentioned logical timing, simulation waveforms will print out (with the No. 1 title on the same PROJECT in). 3. To design a data width of 8bit, the depth is 16 asynchronous FIFO (read and write clock is not the same), when read and write clock frequencies were wrclk = 40MHz, rdclk = 20MHz, the simulation waveform of its logic. Platform: |
Size: 53248 |
Author:李侠 |
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Description: 使用Verilog编写的同步FIFO，可通过设置程序中的DEPTH设置FIFO的深度，FIFO_WRITE_CLOCK上升沿向FIFO中写入数据，
FIFO_READ_CLOCK上升沿读取数据。本程序对FIFO上层操作简单实用。-Prepared by the use of Verilog synchronous FIFO, through the setup program in the FIFO depth DEPTH settings, FIFO_WRITE_CLOCK rising edge to the FIFO write data, FIFO_READ_CLOCK rising edge of read data. This procedure on the upper FIFO operation simple and practical. Platform: |
Size: 1024 |
Author:张键 |
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Description: 用SmartGen生成一个256*8的大小同步FIFO，并通过串口发送数据初始化FIFO。然后，再通过串口返回到上位机的串口调试程序显示，确认数据是否正确。-SmartGen generated with a size of 256* 8 Synchronous FIFO, and sending data through the serial port to initialize FIFO. And then back through the serial port to the PC serial port debugger display to confirm the data is correct. Platform: |
Size: 3072 |
Author:劳杰勇 |
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Description: 一个用verilog实现的同步fifo设计，压缩包里有word介绍设计中各信号的作用-Achieve a synchronous fifo with verilog design, compression bag has the role of word describes the design of the signals Platform: |
Size: 120832 |
Author:csy |
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Description: 用16*8 RAM实现一个同步先进先出（FIFO）队列设计。由写使能端控制该数据流的写入FIFO，并由读使能控制FIFO中数据的读出。写入和读出的操作由时钟的上升沿触发。当FIFO的数据满和空的时候分别设置相应的高电平加以指示(mplementation of a synchronous first in first out (FIFO) queue design with 16*8 RAM. A write FIFO that controls the data stream by writing enable terminals and controls read of data in the FIFO by the read enable. The operation of writing and reading is triggered by the rising edge of the clock. When the data of FIFO is full and empty, set the corresponding high level to indicate) Platform: |
Size: 264192 |
Author:渔火
|
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Description: fifo模块，改模块使用同步fifo设计，里面包含一些设计技巧，读延迟最少(The module of FIFO is modified by using synchronous FIFO, which contains some design skills and the least latency.) Platform: |
Size: 3072 |
Author:林林明 |
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Search - synchronous FIFO