Description: 功能更加完善的基于vhdl的数字时钟设计
有秒表，时钟，时期，闹钟的功能和整点报时，时间调整，日期调整，闹钟的设定
、、、、、、、
秒表有开始，暂停，清零等功能，且只有在暂停的情况下才能清零。-Function more complete VHDL-based design of the digital clock stopwatch, clock, time, alarm clock function and the whole point timekeeping, time adjustment, date, alarm clock settings ,,,,,,, stopwatch has started, pause, Clear and other functions, and only in the case of the suspension can be cleared. Platform: |
Size: 817152 |
Author:张廷 |
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Description: 用VHDL描述一个让6个数码管同时显示的控制器，同时显示0、1、2、3、4、5这6个不同的数字图形到6个数码管上，输入时钟调节频率，使得能够观察到稳定显示的6个数字。可异步复位-Using VHDL description of a six digital tube display controller at the same time, also showed that six different 0,1,2,3,4,5 digital graphics to six digital tube, the input clock frequency adjustment, making it possible to observe the to the stability shown in figure 6. Can be asynchronous reset Platform: |
Size: 1024 |
Author:wx |
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Description: 设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。
实验平台：
1. 一台PC机；
2. MAX+PLUSII10.1。
Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report Platform: |
Size: 425984 |
Author:盼盼 |
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Description: 设计一个具有特定功能的数字电子钟。准确计时，以数字形式显示h、min、s 的时间。小时的计时要求为二十四进位，分和秒的计时要求为六十进位。
该电子钟上电或按键复位后能自动显示系统提示00-00-00，进入时钟准备状态；第一次按电子钟功能键，电子钟从0时0分0秒开始运行，进入时钟运行状态；再次按电子钟功能键，则电子钟进入时钟调整状态，此时可利用各调整键调整时间，调整结束后可按功能键再次进入时钟运行状态。
-Designed with a specific function of a digital electronic clock. Accurate timing to the digital form h, min, s time. Hours of time requested for the 24 binary, minutes, and seconds of time requested for the 60 binary. The electronic bell power or reset button can automatically display 00-00-00 prompted, enter the clock readiness the first time by e-bell function keys, the electronic bell from 00:00:00 to start running, enter the clock running again by e-bell function keys, the electronic bell to enter the clock adjustment status, at this time can use the adjustment button to adjust the time to adjust after the end of function keys can be re-entering the clock running. Platform: |
Size: 6144 |
Author:andy |
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Description: 基于vhdl的数字闹钟的设计。可实现计时、闹钟、调节时间功能。可以在FPGA上实现。-VHDL-based digital alarm clock design. Can achieve a time, alarm clock, adjust time function. FPGA implementation can be on. Platform: |
Size: 2048 |
Author:tony |
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Description: EAD设计VHDL语言环境数字时钟数码管显示方案，包括时间设置、调整等。-VHDL language environment EAD design digital digital clock display, including time for setup, adjustment. Platform: |
Size: 8192 |
Author:王丽 |
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Description: 用VHDL 语言设计数字钟，实现在数码管上显示分钟和秒，并且可以手动调节分钟，
实现分钟的增或者减。该设计包括以下几个部分：
（1）分频电路的设计，产生1Hz 的时钟信号，作为秒计时脉冲；
（2）手动调节电路，包括“时增”“时减”“分增”“分减”。
（3）时分秒计时电路。
（4）7 段数码管显示电路。-Design with VHDL, digital clock, to achieve in the digital display minutes and seconds, and you can manually adjust the minutes, to achieve the increase or decrease minutes. The design includes the following sections: (1) frequency circuit design, produce 1Hz clock signal, as the second timing pulse (2) Manual adjustment circuit, including " the increase" " decrease the time" " point by" " sub- less. " (3), minute and second timing circuits. (4) 7-segment display circuit. Platform: |
Size: 2048 |
Author: |
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Description: 这是一个利用ＶＨＤＬ语言编写的校园打铃系统，它具有正常数字钟功能，通过按键的操作可以实现时间的切换显示与调整，以及春夏与秋冬两季的打铃时间表的切换控制。-This is a campus using VHDL language ring a bell system, which has normal digital clock function, the operation can be achieved through the key switch time display and adjustment, as well as spring and autumn and winter schedule bell switch control. Platform: |
Size: 395264 |
Author: |
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Description: 用VHDL 语言设计数字钟，实现在数码管上显示分钟和秒，并且可以手动调节分钟，
实现分钟的增或者减。该设计包括以下几个部分：
（1）分频电路的设计，产生1Hz 的时钟信号，作为秒计时脉冲；
（2）手动调节电路，包括“时增”“时减”“分增”“分减”。
（3）时分秒计时电路。
（4）7 段数码管显示电路。
将 SW1 和SW2 初始状态均置为高电平。拨动开关SW1 到低，分钟进行加计数，秒停
止计数，当计数到59 时，从00 开始重新加计数，将SW1 拨动到高时，在当前状态进行计时。当拨动开关SW2 为低时，分钟进行减计数，秒停止计数，当减到0 时，从59 开始减计数，将SW2 拨动到高时，在当前状态进行计时。-VHDL language with the design of digital clock, in the digital display minutes and seconds, and can manually adjust the minutes,
To achieve the increase or decrease minutes. The design includes the following sections:
(1) frequency circuit design, resulting in 1Hz clock signal, as the second time pulse
(2) manual adjustment of the circuit, including when the increase when the minus points by sub-minus.
(3) when the minutes and seconds timer circuit.
(4) 7-segment LED display circuit.
Set the initial state of SW1 and SW2 to high level. Toggle switch SW1 to low, minute to count up, seconds to stop
Stop counting, when counting to 59, 00 to re-count the start, will SW1 toggle to high, in the current state of time. When the switch SW2 is low, the timer counts down in minutes and stops counting in seconds. When it decreases to 0, it counts down 59, and turns SW2 to HIGH to count in the current state. Platform: |
Size: 495616 |
Author:panda |
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Description: Xilinx实现电子时钟功能，具有调整时间功能，设置闹钟功能，闹钟播放音乐等，非常适合VHDL入门。-Xilinx implement electronic clock function, have adjustment time function, set the alarm function, the alarm to play music, ideal for entry VHDL. Platform: |
Size: 1517568 |
Author:dong sun |
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