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[USB develop] USB2_chip

Description: USB2.0 chip的一部分verilog源码。opencore上下的，还比较好用:)-USB2.0 chip part of Verilog source. Opencore ish, but also better quality :)
Platform: | Size: 35840 | Author: 戴鹏 | Hits:

[Embeded-SCM Develop] DE2_NIOS_HOST_MOUSE_VGA

Description: 利用该源代码可以实现在DE2的板子上进行USB画笔的实验-use of the source code can be achieved in the board Dictyophora USB brush on the experiment
Platform: | Size: 1024 | Author: 杨阿胡 | Hits:

[VHDL-FPGA-Verilog] CRC-Verilog

Description: 此是进行循环冗余效验的Verilog编码，适合多种标准，如CRC16-this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY
Platform: | Size: 3072 | Author: 藏瑞 | Hits:

[VHDL-FPGA-Verilog] usb_verilog.tar

Description: 文件包含一个usb 专用集成电路设计项目，用的verilog 原码-document contains a usb ASIC design, the original code verilog
Platform: | Size: 197632 | Author: jockeyhao | Hits:

[VHDL-FPGA-Verilog] ccd-in-verilog

Description: ALTERA关于CCD的一些verilog程序，都通过运行无误的。-ALTERA on a number of Verilog CCD procedures, both by running unmistakable.
Platform: | Size: 14336 | Author: 邹振兴 | Hits:

[Other Embeded program] ip

Description: usart的verilog代码.rar 包括很多的FPGA ip 源码，可以直接应用 uart_vhdl.zip sl811usb包含源程序.rar mc8051_design.zip mcpu_1[1].05.zip minicpu.zip mmc_lark_original.zip -USART the Verilog code. rar, including many of the FPGA ip source, can be applied directly uart_vhdl.zipsl811usb contains the source code. rarmc8051_design.zipmcpu_1 [1] .05. zipminicpu.zipmmc_lark_original.zip
Platform: | Size: 5391360 | Author: 钟阳 | Hits:

[VHDL-FPGA-Verilog] FT245_R_W

Description: USB芯片FT245BM读写代码,在Quartus II V7.2上测试成功!---Verilog语言.
Platform: | Size: 1644544 | Author: | Hits:

[VHDL-FPGA-Verilog] usb_funct.tar

Description: Verilog语言描述的USB 2.0接口和新功能固件。-Verilog language description of the USB 2.0 interface and new features in firmware.
Platform: | Size: 198656 | Author: 陈楚龙 | Hits:

[USB develop] usb_funct

Description: usb2.0的Verilog源代码,包含完整的源代码,没有测试激励文件-USB2.0 the Verilog source code, including complete source code, there is no incentive to test document
Platform: | Size: 212992 | Author: 高杰 | Hits:

[Other] usb1.1

Description: USB 1.1的verilog代码，已通过fpga验证-USB 1.1 in Verilog code, has passed through FPGA verification
Platform: | Size: 63488 | Author: zys | Hits:

[Streaming Mpeg4] H.264

Description: 详尽地论述了H.264 特点、编码器原理、解码器原理、编解码器的实现。为了更好地理解H.264 编解码原理及其实现，第7 章详细介绍了H.264 码流的句法和语义。最后对H.264 视频编码传输的QoS 进行了专门地论述。-H.264 are discussed in detail the characteristics of the principle of encoders, decoders principle, the realization of codec. To better understand the H.264 codec principle and its realization, Chapter 7 details H.264 bitstream syntax and semantics. Finally, H.264 video encoding transmission QoS for a special discussion.
Platform: | Size: 4308992 | Author: 王小丫 | Hits:

[USB develop] USB2.0FPGA_EXAMPLES

Description: FPGA与USB通信的测试代码，包括FPGA中的程序（Verilog编写）和PC机上的主控程序以及USB固件程序。-FPGA and the USB communication test code, including the FPGA in the procedure [Verilog prepared] and PC-control procedures, as well as the USB firmware.
Platform: | Size: 5515264 | Author: 李诚铭 | Hits:

[VHDL-FPGA-Verilog] DE2_70_TV

Description: --- --- --- -Verilog--- --- ---- This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor. Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.--------------------Verilog---------------- This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor. Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.
Platform: | Size: 168960 | Author: Sami | Hits:

[VHDL-FPGA-Verilog] uart_tx_rx

Description: 该工程用verilog编写，已通过串口调试助手调试通过，接收模块采用8倍波特率采样数据，有较好的滤波功能，在PC上完成自发自收功能。-Verilog prepared by the project, has passed through the serial debug debugging assistant, receiving 8 times the baud rate module sampling data, a better filtering in the PC to complete the voluntary self-close feature.
Platform: | Size: 1312768 | Author: eric | Hits:

[Other] 68013

Description: 介绍了此控制器与FPGA接口的控制和HDL (硬件描述语言)实现方法。利用CY7C68013控制器的 Slave F IFO从机方式,用Verilog HDL在FPGA中产生相应的控制信号,实现对数据的快速读写。试验 结果表明此方案传输速度快、数据准确,可扩展到其他需要通过USB进行快速数据传输的系统中-This paper describes the controller and the FPGA interface to control and HDL (hardware description language) implementations. Use CY7C68013 controller Slave F IFO slave mode, using Verilog HDL in the FPGA generate a corresponding control signal to achieve fast read and write data. The results show that this program transmission speed, accurate data can be expanded to other needs through the USB for fast data transfer system
Platform: | Size: 365568 | Author: 余岳衡 | Hits:

[VHDL-FPGA-Verilog] WORKS

Description: Project of Adquisition Data, show in VGA and send to usb host
Platform: | Size: 9917440 | Author: lagartojj | Hits:

[Embeded-SCM Develop] NIOS_USB_API_demo

Description: 在nios系统开发中的驱动usb接口芯片的代码,包括verilog代码,与相应的驱动代码-In the nios system development driver usb interface chip of the code, including the verilog code, and the corresponding driver code
Platform: | Size: 1696768 | Author: chd | Hits:

[VHDL-FPGA-Verilog] xtp051_sp601_schematics

Description: Xilinx公司最新的Spartan 6系列FPGA所用的开发板电路图，详尽包括了电源、IO、外设、USB等部分的内容，极具有参考价值，另外还有一个USB芯片 68013所使用的HEX文件可供下载-Xilinx' s new Spartan 6 Series FPGA development board used in circuit detail, including the power, IO, peripherals, USB and some other content, most with a reference value, in addition to a USB chip, 68013 using HEX file available for download
Platform: | Size: 311296 | Author: Frank | Hits:

[Communication] verilog

Description: source code for USB 2.0 fonction core in verilog
Platform: | Size: 57344 | Author: chaitanya | Hits:

[Other] usb

Description: USB slave: It is contain a USB slave design written in verilog language. It is a interface between USB host and Functions such as memory, Keyboard, mouse and so on.-SB slave: It is contain a USB slave design written in verilog language. It is a interface between USB host and Functions such as memory, Keyboard, mouse and so on.
Platform: | Size: 231424 | Author: william | Hits:
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