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Description: verilog加法器产生第0 位本位值和进位值产生第1 位本位值和进位值产生第2 位本位值和进位值
Platform: | Size: 855 | Author: 吕鹏 | Hits:

[Other resource] add

Description: 实现简单十六位加法器及测试程序 的verilog代码
Platform: | Size: 2615 | Author: 舒畅 | Hits:

[Embeded-SCM Develop] add

Description: 自己编制的加法器的verilog程序 希望对大家有所帮助
Platform: | Size: 1518 | Author: 舒畅 | Hits:

[ARM-PowerPC-ColdFire-MIPS] signal_cpu_sort

Description: Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_MEMORY, REGISTER, PC, and TESTBRANCH.-Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_MEMORY, REGISTER, PC, and TESTBRANCH.
Platform: | Size: 8192 | Author: 張大小 | Hits:

[DSP program] bch_euc

Description: bch 编码、解码程序，可以对任意长度的信息添加纠错码。-BCH encoding, decoding procedures can be arbitrary length of the right information to add error-correcting codes.
Platform: | Size: 4096 | Author: Guch Wu | Hits:

[Other Embeded program] NIOS_HOST_MOUSE_VGA

Description: Nios系统, 加入了VGA控制器和USB鼠标控制器-Nios system, add a VGA controller and the USB mouse controller
Platform: | Size: 909312 | Author: | Hits:

[Compress-Decompress algrithms] canbus(FPGA)

Description: 基于FPGA的can 总线设计，采用verilog语言编写。在FPGA的开发环境下，新建一个工程，然后将本文件中的各个源代码添加进工程里，即可运行仿真。-FPGA-based bus design can use verilog language. FPGA development environment, a new project, and then the paper all the source code to add the project, Simulation can be run.
Platform: | Size: 862208 | Author: 李浩 | Hits:

[VHDL-FPGA-Verilog] magnitude

Description: Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm. -Verilog HDL : For a vector magnitude (a, b), the magnitude representation is the following : A common approach to implementing thes e arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonome tric functions of sine, cosine, magn itude, and phase using an iterative process. It i 's made up of a series of micro-rotations of the v ector by a set of predetermined cons tants, which are powers of two. Using binary ar praxiology metic, this algorithm essentially replaces m ultipliers with shift and add operations. In a Stratix
Platform: | Size: 12288 | Author: 郝晋 | Hits:

[Other] add

Description: verilog加法器产生第0 位本位值和进位值产生第1 位本位值和进位值产生第2 位本位值和进位值-Adder Verilog generated the first 0-based values and binary values of the first value and a binary-based values of the first two binary-based value and the value of
Platform: | Size: 1024 | Author: 吕鹏 | Hits:

[VHDL-FPGA-Verilog] add

Description: 介绍了carry_chain_adder，carry_skip_adder,ipple_carry_adder三种常用的加法器，采用verilogHDL语言，利用modelsim软件仿真验证，压缩包中包含有流程图-Introduced carry_chain_adder, carry_skip_adder, ipple_carry_adder three commonly used adder, using verilogHDL language, the use of ModelSim simulation software, compressed packet contains flowchart
Platform: | Size: 372736 | Author: yaoyongshi | Hits:

[VHDL-FPGA-Verilog] add

Description: 实现简单十六位加法器及测试程序 的verilog代码-The realization of a simple adder 16 and the test procedure Verilog code
Platform: | Size: 3072 | Author: 舒畅 | Hits:

[Embeded-SCM Develop] add

Description: 自己编制的加法器的verilog程序 希望对大家有所帮助-Prepared their own Adder Verilog program hopes to help all of you
Platform: | Size: 1024 | Author: 舒畅 | Hits:

[Multimedia program] video_compression_systems.tar

Description: 视频、图像压缩代码，内附使用说明，建立相应工程后，将Verilog代码ADD之后就可以编译调试，对于学习图像压缩或熟悉FPGA调试环境的人员会有一定的帮助-Video, image compression code, containing instructions to establish the corresponding work will Verilog code can be compiled after ADD debugging, for learning image compression, or are familiar with FPGA debug environment will help staff
Platform: | Size: 186368 | Author: 王弋妹 | Hits:

[VHDL-FPGA-Verilog] LowpassfilterVHDLcord

Description: 低通滤波器的VHDL代码，需要的可以下来看看，本人QQ147440013，有志同道合的人可以加我哦-Low-pass filter of the VHDL code, need to take a look at the can down, I QQ147440013, have like-minded people can add me, oh
Platform: | Size: 4096 | Author: 黄建 | Hits:

[SCM] sgs32

Description: Verlog HDL 写得一款32路方波发生器，例子是4路可以自己加，相位可调，频率可调，占空比可调。具体参见readme.doc.此处只提供了源码包含顶层模块sgs32.v 子模块dds.v和pll设置模块altp.v及波形驱动文件-Verlog HDL write a 32 square-wave generator, for example, is able to add 4-way, phase adjustable, adjustable frequency, adjustable duty cycle. See readme.doc. Here only provide a source module that contains the top-level sub-modules sgs32.v settings dds.v and pll module altp.v and waveform-driven document
Platform: | Size: 59392 | Author: TTHR | Hits:

[Software Engineering] pld

Description: 利用QuartusII的"MegaWizard Plug-In Manager", 设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE 把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行 时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。 2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_COUNTER， 设计一个20bit的up_only COUNTER, 要求该COUNTER在FE0FA和FFFFF之间自动循环计数； 分析该COUNTER在EPM7128SLC84-7、EPM7128SLC84-10、和EPF10K70RC240-2、 EPF10K70RC240-4几种芯片中的最大工作频率； 请将计数器的输出值在FFFFC--FE0FF之间的仿真波形打印出来 （仅EPF10K70RC240-4芯片,最大允许Clock频率下）。-QuartusII use the MegaWizard Plug-In Manager , the design of the input data width is 4bit the ADD, SUB, MULT, DIVIDE, COMPARE them as a project, DEVICE selected EPF10K70RC240-4, on their timing simulation, the simulation waveform (input output selected group) in a paper print out. 2. QuartusII use the MegaWizard Plug-In Manager in LPM_COUNTER, the design of a 20bit of up_only COUNTER, requested that the COUNTER in FE0FA and automatic cycle count between FFFFF analysis of the COUNTER in EPM7128SLC84-7, EPM7128SLC84-10, and EPF10K70RC240-2, EPF10K70RC240-4 Several of the largest chip operating frequency I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximum allowable Clock frequency).
Platform: | Size: 31744 | Author: 李侠 | Hits:

[VHDL-FPGA-Verilog] add

Description: Verilog hdl语言 常用加法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used adder design, can use the ModelSim simulation
Platform: | Size: 2048 | Author: 许立宾 | Hits:

[VHDL-FPGA-Verilog] add

Description: 流水线乘法器与加法器 开发环境：Modelsim（verilog hdl）-Multiplier and adder pipeline development environment: Modelsim (verilog hdl)
Platform: | Size: 1024 | Author: 来法旧佛 | Hits:

[Software Engineering] bai2

Description: excercises verilog add two bcd numbers
Platform: | Size: 2287616 | Author: atula136 | Hits:

[VHDL-FPGA-Verilog] add

Description: verilog实现的完整的加法器，包括测试文件等(Verilog implements a complete adder, including test files)
Platform: | Size: 1542144 | Author: inchange | Hits:
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