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[Other] add DL : 0: verilog加法器产生第0 位本位值和进位值产生第1 位本位值和进位值产生第2 位本位值和进位值
Update : 2008-10-13 Size : 855byte Publisher : 吕鹏
[Other resource] add DL : 0: 实现简单十六位加法器及测试程序的verilog代码
Update : 2008-10-13 Size : 2.55kb Publisher : 舒畅
[Embeded-SCM Develop] add DL : 0: 自己编制的加法器的verilog程序希望对大家有所帮助
Update : 2008-10-13 Size : 1.48kb Publisher : 舒畅
[ARM-PowerPC-ColdFire-MIPS] signal_cpu_sort DL : 0: Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_MEMORY, REGISTER, PC, and TESTBRANCH.-Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_MEMORY, REGISTER, PC, and TESTBRANCH.
Update : 2025-02-17 Size : 8kb Publisher : 張大小
[DSP program] bch_euc DL : 1: bch 编码、解码程序，可以对任意长度的信息添加纠错码。-BCH encoding, decoding procedures can be arbitrary length of the right information to add error-correcting codes.
Update : 2025-02-17 Size : 4kb Publisher : Guch Wu
[Other Embeded program] NIOS_HOST_MOUSE_VGA DL : 0: Nios系统, 加入了VGA控制器和USB鼠标控制器-Nios system, add a VGA controller and the USB mouse controller
Update : 2025-02-17 Size : 888kb Publisher :
[Compress-Decompress algrithms] canbus(FPGA) DL : 0: 基于FPGA的can 总线设计，采用verilog语言编写。在FPGA的开发环境下，新建一个工程，然后将本文件中的各个源代码添加进工程里，即可运行仿真。-FPGA-based bus design can use verilog language. FPGA development environment, a new project, and then the paper all the source code to add the project, Simulation can be run.
Update : 2025-02-17 Size : 842kb Publisher : 李浩
[VHDL-FPGA-Verilog] magnitude DL : 0: Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm. -Verilog HDL : For a vector magnitude (a, b), the magnitude representation is the following : A common approach to implementing thes e arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonome tric functions of sine, cosine, magn itude, and phase using an iterative process. It i 's made up of a series of micro-rotations of the v ector by a set of predetermined cons tants, which are powers of two. Using binary ar praxiology metic, this algorithm essentially replaces m ultipliers with shift and add operations. In a Stratix
Update : 2025-02-17 Size : 12kb Publisher : 郝晋
[Other] add DL : 0: verilog加法器产生第0 位本位值和进位值产生第1 位本位值和进位值产生第2 位本位值和进位值-Adder Verilog generated the first 0-based values and binary values of the first value and a binary-based values of the first two binary-based value and the value of
Update : 2025-02-17 Size : 1kb Publisher : 吕鹏
[VHDL-FPGA-Verilog] add DL : 0: 介绍了carry_chain_adder，carry_skip_adder,ipple_carry_adder三种常用的加法器，采用verilogHDL语言，利用modelsim软件仿真验证，压缩包中包含有流程图-Introduced carry_chain_adder, carry_skip_adder, ipple_carry_adder three commonly used adder, using verilogHDL language, the use of ModelSim simulation software, compressed packet contains flowchart
Update : 2025-02-17 Size : 364kb Publisher : yaoyongshi
[VHDL-FPGA-Verilog] add DL : 0: 实现简单十六位加法器及测试程序的verilog代码-The realization of a simple adder 16 and the test procedure Verilog code
Update : 2025-02-17 Size : 3kb Publisher : 舒畅
[Embeded-SCM Develop] add DL : 0: 自己编制的加法器的verilog程序希望对大家有所帮助-Prepared their own Adder Verilog program hopes to help all of you
Update : 2025-02-17 Size : 1kb Publisher : 舒畅
[Multimedia program] video_compression_systems.tar DL : 0: 视频、图像压缩代码，内附使用说明，建立相应工程后，将Verilog代码ADD之后就可以编译调试，对于学习图像压缩或熟悉FPGA调试环境的人员会有一定的帮助-Video, image compression code, containing instructions to establish the corresponding work will Verilog code can be compiled after ADD debugging, for learning image compression, or are familiar with FPGA debug environment will help staff
Update : 2025-02-17 Size : 182kb Publisher : 王弋妹
[VHDL-FPGA-Verilog] LowpassfilterVHDLcord DL : 0: 低通滤波器的VHDL代码，需要的可以下来看看，本人QQ147440013，有志同道合的人可以加我哦-Low-pass filter of the VHDL code, need to take a look at the can down, I QQ147440013, have like-minded people can add me, oh
Update : 2025-02-17 Size : 4kb Publisher : 黄建
[SCM] sgs32 DL : 0: Verlog HDL 写得一款32路方波发生器，例子是4路可以自己加，相位可调，频率可调，占空比可调。具体参见readme.doc.此处只提供了源码包含顶层模块sgs32.v 子模块dds.v和pll设置模块altp.v及波形驱动文件-Verlog HDL write a 32 square-wave generator, for example, is able to add 4-way, phase adjustable, adjustable frequency, adjustable duty cycle. See readme.doc. Here only provide a source module that contains the top-level sub-modules sgs32.v settings dds.v and pll module altp.v and waveform-driven document
Update : 2025-02-17 Size : 58kb Publisher : TTHR
[Software Engineering] pld DL : 0: 利用QuartusII的"MegaWizard Plug-In Manager", 设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE 把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。 2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_COUNTER，设计一个20bit的up_only COUNTER, 要求该COUNTER在FE0FA和FFFFF之间自动循环计数；分析该COUNTER在EPM7128SLC84-7、EPM7128SLC84-10、和EPF10K70RC240-2、 EPF10K70RC240-4几种芯片中的最大工作频率；请将计数器的输出值在FFFFC--FE0FF之间的仿真波形打印出来（仅EPF10K70RC240-4芯片,最大允许Clock频率下）。-QuartusII use the MegaWizard Plug-In Manager , the design of the input data width is 4bit the ADD, SUB, MULT, DIVIDE, COMPARE them as a project, DEVICE selected EPF10K70RC240-4, on their timing simulation, the simulation waveform (input output selected group) in a paper print out. 2. QuartusII use the MegaWizard Plug-In Manager in LPM_COUNTER, the design of a 20bit of up_only COUNTER, requested that the COUNTER in FE0FA and automatic cycle count between FFFFF analysis of the COUNTER in EPM7128SLC84-7, EPM7128SLC84-10, and EPF10K70RC240-2, EPF10K70RC240-4 Several of the largest chip operating frequency I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximum allowable Clock frequency).
Update : 2025-02-17 Size : 31kb Publisher : 李侠
[VHDL-FPGA-Verilog] add DL : 0: Verilog hdl语言常用加法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used adder design, can use the ModelSim simulation
Update : 2025-02-17 Size : 2kb Publisher : 许立宾
[VHDL-FPGA-Verilog] add DL : 0: 流水线乘法器与加法器开发环境：Modelsim（verilog hdl）-Multiplier and adder pipeline development environment: Modelsim (verilog hdl)
Update : 2025-02-17 Size : 1kb Publisher : 来法旧佛
[Software Engineering] bai2 DL : 0: excercises verilog add two bcd numbers
Update : 2025-02-17 Size : 2.18mb Publisher : atula136
[VHDL-FPGA-Verilog] add DL : 0: verilog实现的完整的加法器，包括测试文件等(Verilog implements a complete adder, including test files)
Update : 2025-02-17 Size : 1.47mb Publisher : inchange

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