Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - verilog buffer fifo

Search list

[VHDL-FPGA-Verilog] 9.16fifoasi

Description: 主要完成数字电视前端信号处理和缓冲作用的verilog源代码，可以直接使用 -the major digital TV front-end signal processing and buffer the Verilog source code can be used directly
Platform: | Size: 2761728 | Author: yjb_21cn | Hits:

[VHDL-FPGA-Verilog] fifo8_8

Description:
Platform: | Size: 1024 | Author: 李松 | Hits:

[VHDL-FPGA-Verilog] FIFO_Buffer(verilog)

Description: 这是一个FIFO_Buffer的verilog代码.-This is a FIFO_Buffer the Verilog code.
Platform: | Size: 71680 | Author: 郑海伟 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 先入先出缓冲存储器，采用verilog hdl-FIFO buffer memory, using verilog hdl
Platform: | Size: 2048 | Author: 江浩 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: A First in first out buffer in Verilog
Platform: | Size: 1024 | Author: Ran | Hits:

[Program doc] UART_spec

Description: a UART model with FIFO buffer, design with verilog
Platform: | Size: 145408 | Author: quang | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 运用Verilog 语言对FPGA实现同步的FIFO的数据缓存和传输功能。-FPGA Verilog language used to synchronize the FIFO data buffer and transmission functions.
Platform: | Size: 432128 | Author: 张伟 | Hits:

[VHDL-FPGA-Verilog] SPI

Description: 含有fifo缓冲器的SPI接口源代码，用verilog语言实现-SPI Interface fifo buffer containing the source code, using verilog language
Platform: | Size: 49152 | Author: hechunzhi99 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 异步FIFO Verilog源代码，对控制读写地址进行设计，以便写满和读空只产生一个标志，实现对FIFO的缓冲控制-Asynchronous FIFO Verilog source code, designed to control read and write addresses in order to fill and read empty produce only one flag, the FIFO buffer control
Platform: | Size: 3072 | Author: zx | Hits:

[VHDL-FPGA-Verilog] asynchronous-FIFO-verilog

Description: FIFO是英文First In First Out 的缩写，是一种先进先出的数据缓存器，他与普通存储器的区别是没有外部读写地址线，这样使用起来非常简单-FIFO is an abbreviation of the English First In First Out, is a first-in, first-out data buffer, the difference between him and ordinary memory is external read and write address lines, very simple to use
Platform: | Size: 14336 | Author: chenkun | Hits:

[VHDL-FPGA-Verilog] vga_pannel_design

Description: verilog代码写的控制vga显示的实例，利用状态机进行描述，很好的参考例子-verilog language write serial fifo instance, because the serial port speed is relatively slow, a lot of the interface will use fifo buffer
Platform: | Size: 100352 | Author: 崔帅 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: FIFO，先进先出缓冲器，verilog源代码，包括测试代码。-FIFO, FIFO buffer, verilog source code, including test code.
Platform: | Size: 2048 | Author: 项中元 | Hits:

[VHDL-FPGA-Verilog] parameter_uart_rx

Description: 串口接收模块，可以通过parameter，参数化配置传输速率、传输位宽和校验。采用Verilog语音编程实现。使用者根据串口的要求配置好参数，并根据缓冲的大小配置FIFO就可以使用。对帧错误（停止位不为高），检验错误和读FIFO超时（FIFO满的情况下，有新的数据到）等现象进行了检查。(UART serial receiver module, through parameter, configuration parameters of the transmission rate, Data width and parity. Using Verilog. The user configured the parameters according to the serial port and configured FIFO according to the size of the buffer. The frame error (stop bit is not high), check errors, and read FIFO timeout (when FIFO is full,and new data come) and so on are examined.)
Platform: | Size: 4096 | Author: 老工程师 | Hits:

CodeBus www.codebus.net