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[VHDL-FPGA-Verilog] u-uart

Description: 一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code
Platform: | Size: 5120 | Author: 李文文 | Hits:

[VHDL-FPGA-Verilog] veriloguartrx

Description: verilogHDL编写的串口检测程序，自己写的，相对其他的代码，本程序比较简短，初学者容易掌握。-verilogHDL prepared by serial testing procedures, their own writing, compared with other code, the procedure relatively brief, easy to grasp for beginners.
Platform: | Size: 1024 | Author: | Hits:

[assembly language] lcd_module

Description: verilog code which receive from uart RX and then output to lcd text display.
Platform: | Size: 2048 | Author: 蔡俊仪 | Hits:

[Other Embeded program] UART

Description: 一个通用串口的verilog源程序，包含发送和接收模块-A universal serial Verilog source code, including sending and receiving modules
Platform: | Size: 53248 | Author: typhooncome | Hits:

[VHDL-FPGA-Verilog] Fusion_UART

Description: UART实验Verilog HDL代码，用于FPGA-UART experimental Verilog HDL code for FPGA
Platform: | Size: 3072 | Author: 张猛蛟 | Hits:

[VHDL-FPGA-Verilog] uart(Verilog)

Description: uart异步串口通信协议的源代码，用vhdl语言编写，并且有完整得测试文件-UART asynchronous serial communication protocol source code, using VHDL language, and may have a complete test file
Platform: | Size: 10240 | Author: 阿军 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 串口实验，很好用，我还有verilog HDL VHDL CPLD EPM1270 源代码-Serial experiments, very good, and I still have the source code verilog HDLVHDL CPLDEPM1270
Platform: | Size: 338944 | Author: 韩思贤 | Hits:

[Com Port] UART

Description: 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
Platform: | Size: 9216 | Author: 李佳 | Hits:

[VHDL-FPGA-Verilog] UART_for_FPGArar

Description: it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]-it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]
Platform: | Size: 5120 | Author: yasir ateeq | Hits:

[Software Engineering] lab3

Description: verilog source code for uart design
Platform: | Size: 546816 | Author: Krishna | Hits:

[VHDL-FPGA-Verilog] uart

Description: Verilog编写的UART程序源代码。测试成功。支持字符串发送-UART prepared Verilog source code. Successful test. Support string sent
Platform: | Size: 1548288 | Author: 卢山 | Hits:

[VHDL-FPGA-Verilog] cp_uart_6

Description: 用CPLD驱动UART转USB芯片CP2102的verilog代码，与PC通信包括CP2102的配置驱动等-Using CPLD to drive the USB-UART CP2102 interface. verilog code, then communicate with PC, including the configuration and drivers, etc.
Platform: | Size: 1024 | Author: vicky | Hits:

[VHDL-FPGA-Verilog] UART

Description: verilog代码，串口发送接收代码，含有源代码和测试文件，准确可用-verilog code for serial port transmit and receive code, with source code and test files, and accurate available
Platform: | Size: 7168 | Author: WANGLIN | Hits:

[VHDL-FPGA-Verilog] uart_tx_and_rx

Description: A verilog code for UART transmitter and receiver system-A verilog code for UART transmitter and receiver system...
Platform: | Size: 1024 | Author: EBIN JOY | Hits:

[VHDL-FPGA-Verilog] uart

Description: UART模块的verilog代码，经过测试，能够实现正常的接收和发送功能。-Verilog code for UART module has been tested, it is able to achieve normal receive and transmit functions.
Platform: | Size: 2048 | Author: 郭俊杰 | Hits:

[VHDL-FPGA-Verilog] async.v

Description: verilog code for UART module
Platform: | Size: 2048 | Author: hikem | Hits:

[Other] UART_TX

Description: verilog code for UART
Platform: | Size: 1024 | Author: Humza | Hits:

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[VHDL-FPGA-Verilog] u-uart

[VHDL-FPGA-Verilog] veriloguartrx

[assembly language] lcd_module

[Other Embeded program] UART

[VHDL-FPGA-Verilog] Fusion_UART

[VHDL-FPGA-Verilog] uart(Verilog)

[VHDL-FPGA-Verilog] UART

[Com Port] UART

[VHDL-FPGA-Verilog] UART_for_FPGArar

[Software Engineering] lab3

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] cp_uart_6

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart_tx_and_rx

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] async.v

[Other] UART_TX

[Com Port] uart_verilog

[VHDL-FPGA-Verilog] FPGA-for-UART-source-code

[Other] UART_source_code

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