Search - verilog lab

[Other] Log_Shifter_Gate_Level_Design

Description: Log Shifter Gate Level Design using Verilog(IC design Lab) and Lab Note
Platform: | Size: 2929664 | Author: eknngx | Hits:

[VHDL-FPGA-Verilog] lab

Description:
Platform: | Size: 3980288 | Author: 品十六国 | Hits:

[VHDL-FPGA-Verilog] VerilogLabSource

Description: Verilog Lab Source Codes
Platform: | Size: 2048 | Author: omid | Hits:

[Industry research] Verilog+lab+3+-+HTN+lab+2

Description: a lab by vhdl, let discover and enjoy it now
Platform: | Size: 1666048 | Author: huỳ nh an | Hits:

Description: 一个多周期CPU的完整设计，quartus平台，Verilog实现，内含实验报告，和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
Platform: | Size: 6606848 | Author: 涯 | Hits:

[VHDL-FPGA-Verilog] 86verilog

Description: 以FPGA 芯片为平台构建了数字信号滤波实时处理模块, 给出了 50Hz 陷波器的切比雪夫Ê 型 IIR 数字滤波器 4 阶级联的结构, 提出了对滤波器系数量化的逼近方法, 完成了基于 FPGA 的陷波器实现, 并成功地实现了对含有工频 50Hz 噪声干扰的心电信号的滤波处理, 通过与M at lab 计算所得到的滤波处理效果进行比较分析, 结果表明: 基于FPGA 采用切比雪夫Ê 型 4 级级联结构的 IIR 数字滤波器的误差满足设计要求-　W ith the development of the techno logy of VL S I, the techno logy fo r digital signal p rocessing has developed rap idly . In th is paper, the arch itecture of 50Hz four th2 o rder Chebyshev′ s ModelÊ digital f ilter is show n . In the same t i me, themethod fo r f ilter coeff icient quant if icat i on is p resented . How ever, the f ilter based on FPGA is i mp lemented . The f ilter can p rocess digital signal successfully and its perfo rmance sat isf ies w ith design requirement .
Platform: | Size: 15360 | Author: 任伟 | Hits:

[VHDL-FPGA-Verilog] lab

Description: verilog语言设计同步加法器，异步减法器，16位计数器-adder verilog language design synchronous, asynchronous subtractor, 16-bit counter
Platform: | Size: 762880 | Author: 白叶叶 | Hits:

[VHDL-FPGA-Verilog] verilog-programs

Description: These are first programs of my asic and fpgas lab.This folder contains simple half adder and its test bench using verilog language.Then it also contains 4 to 1 mux using two 2 to 1 muxes.Then its also has its test bench to check the code.These programs are really help ful for those who want to start the learning of verilog language.
Platform: | Size: 2048 | Author: gul | Hits:

[Software Engineering] eda-verilog-report

Description: EDA的实验报告，有六个入门级实验，写得比较详细，方便大家学习，传阅-EDA lab reports, there are six entry-level experiment, written in more detail, to facilitate learning, circulated
Platform: | Size: 347136 | Author: 张建炀 | Hits:

[VHDL-FPGA-Verilog] lab1_Verilog

Description: verilog lab 是一个verilog 的实验文件，是初学者的学习材料。-verilog verilog lab is an experiment file, a beginner' s learning materials.
Platform: | Size: 52224 | Author: huerpei | Hits:

[VHDL-FPGA-Verilog] computer-architecture-lab

Description: this document explain the majors of VERILOG language in a very efficient and briefly manner.this is very useful to learn about hardware design and implementing them by FPGAs.
Platform: | Size: 201728 | Author: mehdi | Hits:

[VHDL-FPGA-Verilog] m.e-lab

Description: vhdl verilog code for alu operation pll,biy sliced processor
Platform: | Size: 6144 | Author: suganya | Hits:

[VHDL-FPGA-Verilog] LAB-1

Description: 用组合电路实现的ROM,编程环境为QUARTUS II，verilog编写的例程。-The combinational circuit ROM programming environment QUARTUS II, verilog written routines.
Platform: | Size: 223232 | Author: 李娟 | Hits:

[VHDL-FPGA-Verilog] LAB-2

Description: 用FPGA实现对VGA的控制，没有用到niosII,只是用硬件描述语言verilog。整个工程。-With FPGA VGA control is not used niosII, just verilog hardware description language. The entire project.
Platform: | Size: 3118080 | Author: 李娟 | Hits:

[VHDL-FPGA-Verilog] LAB-15

Description: FPGA实现对电梯的设计，verilog实现的。-FPGA implementation of the design of the elevator, verilog achieved.
Platform: | Size: 516096 | Author: 李娟 | Hits:

[VHDL-FPGA-Verilog] LAB-16

Description: 用FPGA实现的性线反馈移位寄存器（LFSR）设计。整个工程在quartusII环境下，用verilog编程。-FPGA implementation of the line feedback shift register (LFSR) design. The whole project in verilog programming the quartusII environment.
Platform: | Size: 304128 | Author: 李娟 | Hits:

[Other] coa lab

Description: lab assignmenbt in verilog
Platform: | Size: 516096 | Author: kgp | Hits:

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[Other] Log_Shifter_Gate_Level_Design

[VHDL-FPGA-Verilog] lab

[VHDL-FPGA-Verilog] VerilogLabSource

[Industry research] Verilog+lab+3+-+HTN+lab+2

[VHDL-FPGA-Verilog] CPU

[VHDL-FPGA-Verilog] 86verilog

[VHDL-FPGA-Verilog] lab

[VHDL-FPGA-Verilog] verilog-programs

[Software Engineering] eda-verilog-report

[VHDL-FPGA-Verilog] lab1_Verilog

[VHDL-FPGA-Verilog] computer-architecture-lab

[VHDL-FPGA-Verilog] m.e-lab

[VHDL-FPGA-Verilog] LAB-1

[VHDL-FPGA-Verilog] LAB-2

[VHDL-FPGA-Verilog] LAB-15

[VHDL-FPGA-Verilog] LAB-16

[Other] coa lab

[Documents] Lab1_Skeleton.tar

[Windows Develop] lab0_32

[VHDL-FPGA-Verilog] Verilog数字VLSI设计教程（源码）

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