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Description: VHDL 关于2DFFT设计程序
u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be
seen in the following section.
u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus
network, and it support these sub-modules scinode1∼ scinode9 reset and clk
and global_cnt signals to synchronous the sub-modules to simplify the overall
design.
u proj2.wfc: VSS simulation result that is the same as the ModelSim simulation
result.
u Pro2_2.wfc: VSS simulation result of another test pattern can’t cause overflow
situation.-VHDL design procedures on 2DFFT u scinode1
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Size: 783360 |
Author: 李成 |
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Description: 显卡中关于3D图形处理的源码，是VHDL版本的
喜欢硬件FPGA图像处理的可以看看，挺有意思-Graphics 3D graphics on the source, is like VHDL version of the FPGA hardware image processing can see quite interesting
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Size: 1686528 |
Author: dido wang |
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Description: 一个网络控制的物理层控制程序,-a network control of the physical layer control procedures,
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Size: 8192 |
Author: zlw |
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Description: 详细描述了DM9000A网络接口芯片的功能，对于DE2开发板上的学习很有帮助。还上载了C程序的实现以及Verilog 代码的实现，-DM9000A described in detail the functions of network interface chip, for DE2 development board very helpful. Also upload a C procedure, as well as realize realize Verilog code,
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Size: 2657280 |
Author: 周莹 |
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Description: 实现一个网卡的功能。介绍了怎样从第二层上开发网络接口，并且怎么样第一层的物理层相连接以及如何与ip曾相互之间通讯。-Realize the function of a network adapter. Introduction how to develop from the second network interface layer and the first level how to connect the physical layer and how communication between ip have.
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Size: 122880 |
Author: xiexiao |
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Description: 介绍如何用FPGA实现网络视频传输的设计论文，很有参考价值。-Introduce how to realize the network video transmission FPGA design papers, a good reference.
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Size: 190464 |
Author: 曾祥进 |
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Description: This paper presents the results of the Finnish national "Technology Vision of the Future Distribution Network" project. The aim of the project was to create a technology vision of future distribution networks. Because the life span of networks is very long, a long term vision is very important for guiding network investments and technology development.
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Size: 345088 |
Author: 何平 |
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Description: 低频相位测量系统，包括相位测量仪、数字式移相信号发生器和移相网络三部分-Low-frequency phase measurement system, including the phase-measuring instrument, digital shift believe that its generator and phase-shifting network of three parts
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Size: 18432 |
Author: 郑淑琴 |
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Description: FPGA神经网络设计（影印本），全英文，很有用-FPGA neural network design (photocopies), all in English, very useful
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Size: 3940352 |
Author: ln |
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Description: 针对嵌入式系统的底层网络接口给出了一种由FPGA实现的以太网控制器的设计方法．该控制器能支持10Mbps和100Mbps的传输速率以及半双工和全双工模式，同时可提供MII接口，可并通过外接以太网物理层（PHY）芯片来实现网络接入
-Embedded systems for the bottom of this paper, a network interface from FPGA to achieve the Ethernet controller design method. The controller will support the 10Mbps and 100Mbps transfer rate, as well as half-duplex and full-duplex mode, at the same time provides MII interface, and through external Ethernet physical layer (PHY) chip to achieve network access
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Size: 316416 |
Author: 林大朋 |
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Description: 这是我在ISP编程实验中独立编写的采用结构化描述的一个七人表决器，通过独特的3次映射一位全加器的方法从而实现七人表决器的功能，与网络上任何其他的七人表决器源码决无雷同。-This is my ISP programming in an independent experiment using a structured, prepared as described in a seven-member voting machine, through a unique 3 times a full adder mapping method in order to achieve a vote of seven functions, with the network on any other A seven-member voting machine source code must not identical.
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Size: 84992 |
Author: daisichong |
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Description: 神经网络算法的FPGA实现，英文版，具有很强的实用价值-Neural network algorithm to achieve the FPGA, in English, has a strong practical value
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Size: 3942400 |
Author: HENRRY |
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Description: protus的人们必备，是从网络上摘录的经典-people must protus is extracted from the network on a classic
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Size: 705536 |
Author: nanyuanqi |
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Description: ALTERA Nios II Embedded Evaluation Kit开发板制造商(terasic)提供的多媒体显示板（Terasic Multimedia Touch Panel
Daughter Board (MTDB)）扩展开发包。
里为有两个开源的例子
1.MTDB_SD_Card_Audio,从SD卡中读取WAV文件然后通过DA播放，这个对不SD Card的初学者非常的有用，可以知道使用FPGA SPI来读写SD CARD。
2.MTDB_Systhesizer,使用FPGA来做电子琴，要用FPGA来做合成器的看这个。
国内部分地区的网络对TERASIC封杀，原因不明，这个包是使用代理下载的，非常不容易。-ALTERA Nios II Embedded Evaluation Kit development board manufacturers (terasic) to provide multi-media display boards (Terasic Multimedia Touch Panel Daughter Board (MTDB)) the expansion of the development package. Where for example there are two open source 1.MTDB_SD_Card_Audio, from the SD card and then read the WAV file to play through the DA, the SD Card for the beginner is not very useful, we can see that the use of FPGA SPI read and write to SD CARD. 2.MTDB_Systhesizer, the use of FPGA as organ, synthesizer use FPGA to do the look at this. Internal parts of the network to block TERASIC for reasons unknown, the package is downloaded using a proxy, is not easy.
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Size: 27464704 |
Author: myfingerhurt |
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Description: 关于自动售货机的报告，内有源程序和DC综合网表图-Report on the vending machine with a DC source and an integrated network chart
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Size: 560128 |
Author: 小阳 |
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Description: 自己写一个关于维mesh结构的noc网络，verilog，仿真结果无误。-Write their own structure on the noc-dimensional mesh network, verilog, accurate simulation results.
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Size: 95232 |
Author: 巴音 |
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Description: 模拟网络串行通信 近期对计算机间通信比较感兴趣，同时研究usb通信原理，起步为串行通信于是想为更好地理解其机理做一定基础性研究，故做了异步串行通信设计实验。
经过QUARTUS验证，获得了一等奖！-Simulation of the recent serial communication network between the communication of more interested in computers, communications usb at the same time the principle of starting for serial communication therefore would like to better understand the mechanism to do some basic research, it has done the design of asynchronous serial communication experiment . After verification QUARTUS obtained the first prize!
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Size: 1860608 |
Author: ayls |
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Description: VHDL IP Stack: This IP stack for an FPGA is a complex design because of the number of layers and the complexity of each that is required. It is limited to 10Mb/s operation and is designed for a full duplex switched network. It implements the lower layers of a standard TCP/IP stack. Further implementation is needed to make it work specifically for a certain purpose (eg a web server). There is support to read and write to RAM from the PC via the parallel port as well, for debugging and tests purposes (this maybe easily removed). Note the design only supports IP and ARP frames, other protocols such as RARP and 802.2 frames are not supported.-VHDL IP Stack: This IP stack for an FPGA is a complex design because of the number of layers and the complexity of each that is required. It is limited to 10Mb/s operation and is designed for a full duplex switched network. It implements the lower layers of a standard TCP/IP stack. Further implementation is needed to make it work specifically for a certain purpose (eg a web server). There is support to read and write to RAM from the PC via the parallel port as well, for debugging and tests purposes (this maybe easily removed). Note the design only supports IP and ARP frames, other protocols such as RARP and 802.2 frames are not supported.
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Size: 81920 |
Author: James |
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Description: vhdl network links and main key for installation
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Size: 723968 |
Author: Manikandan |
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Description: Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks.
External hardware accelerator is used for network packet processing. The common network tasks include CRC and Checksum calculations that are used for validation of data integrity in the network packets.
The accelerator unit is able to perform a checksum and CRC calculation autonomously without CPU interactions using a build in DMA mechanism.
-Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks.
External hardware accelerator is used for network packet processing. The common network tasks include CRC and Checksum calculations that are used for validation of data integrity in the network packets.
The accelerator unit is able to perform a checksum and CRC calculation autonomously without CPU interactions using a build in DMA mechanism.
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Size: 2388992 |
Author: Amit Adoni |
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