Search - vhdl risc

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[VHDL-FPGA-Verilog] 靳远－源程序 DL : 0: 几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码-several VHDL source code, and in my preparation of a five pipelined RISC CPU code
Update : 2025-02-17 Size : 433kb Publisher : core_design
[SCM] VHDL实现简单的8位CPU2 DL : 0: 用VHDL实现8位的单片机！里面有开发过程和代码阿！很详细的哦-using VHDL eight of SCM! Inside the development process and code Ah! Detailed oh
Update : 2025-02-17 Size : 52kb Publisher : 冯海
[VHDL-FPGA-Verilog] VHDL例程 DL : 0: 有关VHDL的大量例程，对学习VHDL编程的人具有很大的帮助，不可不看-lot of routines, to learn VHDL programming of great help, I can not see
Update : 2025-02-17 Size : 165kb Publisher : 周
[VHDL-FPGA-Verilog] RISC DL : 0: hrisc cpu，为何只有vhdl选择呢？大家都用verilog的啊-hrisc cpu why only VHDL choice? We all use the Verilog ah
Update : 2025-02-17 Size : 125kb Publisher : 12
[File Format] jiyuVHDLdeIPheyanzheng DL : 0: 摘要探讨了IP 核的验证与测试的方法及其和 VHDL语言在 IC 设计中的应用并给出了其在RISC8 框架 CPU 核中的下载实例．-Abstract IP nuclear testing and certification of the method and its VHDL and in IC Design and Application given its RISC8 framework in the CPU core downloaded example.
Update : 2025-02-17 Size : 116kb Publisher : 赵天
[VHDL-FPGA-Verilog] risc-8 DL : 0: 一个VHDL实现的RISC8位单片机-the RISC8 bit microcontrollers
Update : 2025-02-17 Size : 75kb Publisher : 刘恩树
[VHDL-FPGA-Verilog] alu DL : 0: 16位RISC CPU的ALU，使用VHDL编写-16-bit RISC CPU
Update : 2025-02-17 Size : 2kb Publisher : 李斌
[VHDL-FPGA-Verilog] RiscCPU8 DL : 0: 可综合的VerilogHDL设计实例: ---简化的RISC 8位CPU设计简介--- -VerilogHDL be integrated design example:--- simplified RISC 8 bit CPU design Introduction---
Update : 2025-02-17 Size : 214kb Publisher : hulin
[VHDL-FPGA-Verilog] risc_cpu DL : 0: 8位risc cpu的编写，使用quartus软件对其进行写入，里面内置乘法器、除法器等模块-8-bit risc cpu the preparation, use the Quartus software to write, which built-in multiplier, divider modules
Update : 2025-02-17 Size : 795kb Publisher : 瑞翔
[VHDL-FPGA-Verilog] RISC_CPU DL : 0: RISC CPU IP CORE 可以用于直接的工程开发应用有详细的说明书-RISC CPU IP CORE can be used to direct the development and application of the project has a detailed brochure
Update : 2025-02-17 Size : 561kb Publisher : 毋杰
[VHDL-FPGA-Verilog] verilog_risc DL : 0: RISC状态机由三个功能单元构成：处理器、控制器和存储器。 RISC状态机经优化可实现高效的流水线操作。 RISC 中的数据线为16位。在数据存储器中的0到15的位置放置16个随机数，求16个数的和，放在数据存储器的16、17的位置，高位在前对这16个数进行排序，从大到小放置在18到33的位置求出前16个数的平均数，放在34的位置基本指令有NOP, ADD, SUB, AND, RD, WR, BR,BC。因为采用16位指令，有扩充的余地。-RISC state machine consists of three functional modules: processor, controller and memory. RISC state machine can be realized by optimizing the efficient pipelining. RISC data in line 16. In the data memory in the 0-15 position placed 16 random numbers, and the number 16 and, on the data memory of the 16,17 position, the previous high of 16 the number of these sort, smallest place in the 18-33 position to derive the average number of the top 16, on the location of 34 basic instructions are NOP, ADD, SUB, AND, RD, WR, BR, BC. Because the use of 16-bit instructions, there is room for expansion.
Update : 2025-02-17 Size : 126kb Publisher : lyn
[Other] RiscCpu DL : 1: Verilog-RISC CPU 代码实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware description language, and design methods. The procedure adopted ModelSim simulation. BUAA
Update : 2025-02-17 Size : 9kb Publisher : sss
[ARM-PowerPC-ColdFire-MIPS] risc DL : 0: 嵌入式risc处理器源码，包含设计文档，原理图，testbench，及外围接口，使用verilog实现。-Source embedded RISC processors, including design documents, schematics, testbench, and peripheral interfaces, the use of Verilog to achieve.
Update : 2025-02-17 Size : 126kb Publisher : 李林
[VHDL-FPGA-Verilog] 32bit_RISC_CPU DL : 1: 32 risc cpu的参考设计，内涵完整的testbench-32 risc cpu s reference design, the connotation of complete Testbench
Update : 2025-02-17 Size : 2.33mb Publisher : zys
[VHDL-FPGA-Verilog] freerisc8_11 DL : 0: 一个基于VHDL 的简单8位CPU的IP core核心代码-VHDL based on a simple 8-bit CPU core code of the IP core
Update : 2025-02-17 Size : 269kb Publisher : wfs
[VHDL-FPGA-Verilog] OR1200_verilog DL : 0: or1200开源risc cpu的verilog描述实现，cpu源代码分析与芯片设计一书的源码-or1200 open source Verilog description of the risc cpu realize, cpu source code analysis and chip design source book
Update : 2025-02-17 Size : 200kb Publisher : yu
[VHDL-FPGA-Verilog] risc DL : 0: RISC（reduced instruction setcomputer，精简指令集计算机）是一种执行较少类型计算机指令的微处理器。改源码是vhdl语言，能在FPGA上跑。-RISC [reduced instruction setcomputer, Reduced Instruction Set Computer] is an implementation of fewer types of computer instructions to the microprocessor. VHDL source code are changed language in the FPGA on the run.
Update : 2025-02-17 Size : 9kb Publisher : zhang
[Windows Develop] RISC_8 DL : 0: 经过验证的8位RISC-CPU源代码，verilog代码，附：汇编测试源代码，而且测试通过。-Verified 8 RISC-CPU source code, verilog code, attached: the compilation of the test source code, and test.
Update : 2025-02-17 Size : 169kb Publisher : WangYong
[VHDL-FPGA-Verilog] risc DL : 0: 用Verilog 编写的8位risc cpu，行为级描述，可综合-6 bits risc cpu by Verilog
Update : 2025-02-17 Size : 129kb Publisher : 徐明
[VHDL-FPGA-Verilog] RISC DL : 0: source and benchmark test for the registery parts of a RISC processor-source and benchmark test for the registery parts of a RISC processor
Update : 2025-02-17 Size : 155kb Publisher : radproject

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