Search - waveform vhdl

[Other resource] 一些VHDL源代码

Description: 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Platform: | Size: 45110 | Author: 蔡孟颖 | Hits:

[Other resource] three-vhdl

Description: VHDL下实现3分频率波形,完整源代码,学习参考-VHDL under three frequency waveform, complete source code, study reference
Platform: | Size: 96880 | Author: 陈度甫 | Hits:

[VHDL-FPGA-Verilog] 数字频率计实验报告

Description: 课程设计要求设计并用FPGA实现一个数字频率计，具体设计要求如下：测量频率范围： 10Hz～100KHz 精度： ΔF / F ≤ ±2 % 系统外部时钟： 1024Hz 测量波形：方波 Vp-p ＝ 3～5 V 硬件设备：Altera Flex10K10 五位数码管 LED发光二极管编程语言：Verilog HDL / VHDL-curriculum design and FPGA design to achieve a digital frequency meter, the specific design requirements are as follows : measurement frequency range : 10Hz to 100KHz precision : F/F 2% external clock system : 1024Hz Waveform Measurement : square Vp-p = 3 ~ 5 V hardware : Altera Flex10K10 five digital LED light emitting diode programming languages : Verilog HDL/VHDL
Platform: | Size: 144384 | Author: 兰 | Hits:

[VHDL-FPGA-Verilog] 一些VHDL源代码

[Other] autosale

Description: VHDL编写的自动售货机，带找零、退币功能，数字电路课程设计！内附常态图，和dofile波形模拟文件-VHDL prepared by the vending machines, have sought to bring, the coin features, digital circuit design courses! Enclosing normal map and document dofile waveform simulation
Platform: | Size: 3072 | Author: 张傻 | Hits:

[Other] trafficlight

Description: VHDL编写的交通灯程序，有倒计时功能，数字电路课程设计，内附状态图和dofile波形模拟！-VHDL prepared by the traffic lights procedures, the countdown function, digital circuit design courses, enclosing a state map and dofile waveform simulation!
Platform: | Size: 4096 | Author: 张傻 | Hits:

[VHDL-FPGA-Verilog] 一个波形发生器和sine波形发生器

Description: 这是一个典型的正玄波发生器程序和一个任意波形发生器程序，大家可以参考学习，对于vhdl入门还是很有帮助的-This is a typical wave generator Shogen procedures and an arbitrary waveform generator procedures, Members can take a learning portal for VHDL or helpful
Platform: | Size: 3072 | Author: 张云鹏 | Hits:

[VHDL-FPGA-Verilog] three-vhdl

Description: VHDL下实现3分频率波形,完整源代码,学习参考-VHDL under three frequency waveform, complete source code, study reference
Platform: | Size: 96256 | Author: 陈度甫 | Hits:

[VHDL-FPGA-Verilog] DDS234

Description: 文中给出了用VHDL实现三角波正弦波方波的代码, 可以在maxPLUX2上运行,-In this paper, using the VHDL-wave sine wave square wave triangle realize the code, you can run maxPLUX2,
Platform: | Size: 2048 | Author: qibinchuan | Hits:

[Algorithm] VHDL

Description: 此代码可产生正弦波、三角波、正斜率拨、负斜率波波、矩形波五种波形-This code can generate sine wave, triangle wave, the slope is allocated, the negative slope of the ball, five rectangular-wave waveform
Platform: | Size: 1024 | Author: 刘三平 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成各种波形的线形叠加输出。 -Realize four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency, magnitude controllable output (square wave A, is also a controllable duty cycle), can store arbitrary waveform feature data and can reproduce the waveform, but also completed a variety of linear superposition of the output waveform.
Platform: | Size: 9216 | Author: zhanyi | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 用vhdl语言编写的基于FPGA的波形发生器。对于做实验需要产生的波形非常有用。-VHDL language using FPGA-based waveform generator. Does the need for experimental waveforms generated very useful.
Platform: | Size: 1736704 | Author: 姚大雷 | Hits:

[VHDL-FPGA-Verilog] 1111

Description: 基于FPGA的多波形发生器基于FPGA的多波形发生器-FPGA-based multi-waveform generator based on multi-FPGA Waveform Generator
Platform: | Size: 1073152 | Author: 刘明吉 | Hits:

[VHDL-FPGA-Verilog] VHDL-ROM4

Description: 基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), waveform generator control module and latch module 2. Waveform data storage module (ROM) custom data width of 8 , address width of 6, can store 64 points sinusoidal waveform data, waveform data are obtained using MATLAB. 3. To 50MHz clock as input.
Platform: | Size: 98304 | Author: 宫逢源 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: PWM控制就是产生一定周期，占空比不同的方波信号，当占空比较大时，电机转速较高，否则电机转速较低。当采用FPGA产生PWM波形时，只需FPGA内部资源就可以实现，数字比较器的一端接设定值输出，另一端接线性递增计数器输出。当线性计数器的计数值小于设定值时输出低电平，当计数器大于设定值时输出高电平，这样就可通过改变设定值，产生占空比不同的方波信号，从而达到控制直流电机转速的目的。直流电机控制电路主要由2部分组成，如图1所示：  FPGA中PWM脉宽调制信号产生电路；  FPGA中正/反转方向控制电路 -PWM control is a certain cycle, a different duty cycle square wave signal, when the duty cycle is high, higher motor speed, or lower motor speed. When the PWM waveform generated using FPGA, the FPGA internal resources only can be achieved, the figure one comparator output termination setting, the other linear incremental counter output termination. When the value of linear counter output is less than low-level settings, when the counter output is greater than high settings, so that by changing the settings can produce different duty cycle square wave signal, DC motor control to achieve the purpose of speed. DC motor control circuit mainly by 2 parts, as shown in Figure 1:  FPGA in the PWM pulse width modulation signal generator circuit Chiang Kai-shek  FPGA/reverse direction control circuit
Platform: | Size: 37888 | Author: 袁玉佳 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: DEMO2 数码管扫描显示电路/DEMO4 计数时钟 DEMO5 键盘扫描设计/DEMO6 波形发生器/DEMO7 用DAC实现电压信号检测/DEMO8 ADC电压测量/DEMO9 液晶驱动电路设计-DEMO2 digital tube display circuit scan/DEMO4 count clock scan design DEMO5 keyboard/DEMO6 Waveform Generator/DEMO7 implementation by DAC voltage signal detection/DEMO8 ADC voltage measurement/DEMO9 LCD driver circuit design
Platform: | Size: 736256 | Author: wang | Hits:

[VHDL-FPGA-Verilog] sWave

Description: 正弦波，Verilog波形发生器，很好的东西-Sine wave, Verilog waveform generator, a good thing
Platform: | Size: 1391616 | Author: yanppf | Hits:

[VHDL-FPGA-Verilog] waveform

Description: 自己做的一个波形发生器，有兴趣的可以看下-Myself as a waveform generator may be interested in Kanxia
Platform: | Size: 119808 | Author: 周宇 | Hits:

[VHDL-FPGA-Verilog] VHDL(sin)

Description: 基于ROM的正弦波发生器的设计一．实验目的 1. 学习VHDL的综合设计应用 2. 学习基于ROM的正弦波发生器的设计二．实验内容设计基于ROM的正弦波发生器，对其编译，仿真。具体要求： 1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based sine wave generator design 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning ROM-based sine wave generator design 2. Experimental content ROM-based sine wave generator design, its compilation, simulation. Specific requirements: 1. Sine wave generator by the data storage module (ROM), waveform generator control module and latch modules Two. Waveform data storage module (ROM) custom data width is 8, the address width of 6, can store 64-point sine wave data, wave data obtained using MATLAB. 3. The 50MHz input clock.
Platform: | Size: 17408 | Author: 爱好 | Hits:

[VHDL-FPGA-Verilog] FPGA-VHDL-DDS

Description: 基于FPGA的DDS波形发生器--程序，如果需要产生输出不同的位数的波形，可以自行修改程序中的rom表中数据位数-FPGA-based waveform generator DDS- procedure, if the number of bits required to generate output of different waveforms in the program can modify data in the table the median rom
Platform: | Size: 1256448 | Author: 许聪 | Hits:

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[Other resource] 一些VHDL源代码

[Other resource] three-vhdl

[VHDL-FPGA-Verilog] 数字频率计实验报告

[VHDL-FPGA-Verilog] 一些VHDL源代码

[Other] autosale

[Other] trafficlight

[VHDL-FPGA-Verilog] 一个波形发生器和sine波形发生器

[VHDL-FPGA-Verilog] three-vhdl

[VHDL-FPGA-Verilog] DDS234

[Algorithm] VHDL

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] 1111

[VHDL-FPGA-Verilog] VHDL-ROM4

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] sWave

[VHDL-FPGA-Verilog] waveform

[VHDL-FPGA-Verilog] VHDL(sin)

[VHDL-FPGA-Verilog] FPGA-VHDL-DDS

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