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VHDL-FPGA-Verilog list
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适用各种体制的RS编码,Verilog实现,配置本原多项式参数即可
Update : 2019-08-29 Size : 1.71kb Publisher : 1314@someone

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nexys3--ucf is the ucf file for nexys3 board
Update : 2019-09-06 Size : 4.08kb Publisher : jcljob

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shi xian yun dong jian ce .
Update : 2024-12-22 Size : 13kb Publisher : zero_lz

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AHB master behavior level model, AHB slave model
Update : 2024-12-22 Size : 2kb Publisher : 鱼在在藻

Verilog implementation of priority rotation algorithm with weight
Update : 2024-12-22 Size : 427kb Publisher : 鱼在在藻

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Verilog implementation of a median filtering algorithm
Update : 2024-12-22 Size : 4kb Publisher : 兴鹏

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Realize the camera ov7725 acquisition of video, output through VGA port. Fpga model EGO1, you can modify the XDC file.
Update : 2024-12-22 Size : 14.39mb Publisher : beTTer_every

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Huffman compression implemented by Verilog
Update : 2024-12-22 Size : 74kb Publisher : 实现那是

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transition of A/D signal
Update : 2024-12-22 Size : 12.05mb Publisher : 白珑

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use verilog to trans PDM to PCM signal,use vivado
Update : 2024-12-22 Size : 6.9mb Publisher : hcccc1117

Verilog frequency meter program of xc7a35tcsg324-1 supports decadal frequency division and switching internal and external signal input
Update : 2024-12-22 Size : 23kb Publisher : wanzaiwharf

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sgmii use verilog coding,and can work 1000M ethernet
Update : 2024-12-22 Size : 947kb Publisher : caohy168
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