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VHDL-FPGA-Verilog list
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AD5764 configuration program, written in verilog, I hope to help everyone
Update : 2024-12-22 Size : 6.68mb Publisher : SUBZERO

Verilog Digital VLSI Design Course Official Lab
Update : 2024-12-22 Size : 10.95mb Publisher : brico

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The PID algorithm is implemented in Verilog language. The actual measurement is available. It consists of three modules.
Update : 2024-12-22 Size : 1kb Publisher : wrnd

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The adaptive equalizer based on the symbol LMS algorithm is simulated. The performance simulation of the algorithm is required, the input signal for FPGA test is generated, and the data range of simulation weight in the
Update : 2024-12-22 Size : 928kb Publisher : SEXYLADY

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Design a 1MHz FIR low pass filter. Requirements: (1) clock signal frequency 16MHz; (2) input signal bit width of 8bits, symbol rate of 16MHz Requirements in Matlab FIR filter floating-point and fixed-point simulation, an
Update : 2024-12-22 Size : 334kb Publisher : 羊羊驼

Design a 1MHz FIR low pass filter. Huffman coding is required for a section of data sequence to make the average code length the shortest, and the output of each element encoding and the encoded data sequence. The elemen
Update : 2024-12-22 Size : 178kb Publisher : 羊羊驼

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Verilog implementation of HDMI protocol, through TMDS coding of RGB three channels, pure original code
Update : 2024-12-22 Size : 7kb Publisher : frostmorne

Solutions for computer experiment.
Update : 2024-12-22 Size : 33.2mb Publisher : 陈惜

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rgb to YCbCr converter
Update : 2024-12-22 Size : 4.61mb Publisher : Kevaen

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Program for sending data from computer and receiving data by FPGA, UART module
Update : 2024-12-22 Size : 17.55mb Publisher : godxun

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Verilog code writing and simulation files for brick-blocking games
Update : 2024-12-22 Size : 6kb Publisher : simplewqq

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The DE2-115 board is shipped from the factory with a default configuration bit-stream that demonstrates some of the basic features of the board.
Update : 2024-12-22 Size : 3.01mb Publisher : 流火守夜人
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