VHDL-FPGA-Verilog List Page 327

VHDL-FPGA-Verilog list

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parall_interf Downloaded：0: Serial Peripheral Interface
Update : 2025-01-16 Size : 1kb Publisher : 李长兴
design Downloaded：0: Floating point numbers are rational numbers belonging to a particular subset of the digital representation for an approximate representation of any real number in the computer.
Update : 2025-01-16 Size : 2kb Publisher : 李长兴
ADC_READ Downloaded：0: ADC read，Einlesen der Daten von ADC-Wandler dann in FIFO Speichern
Update : 2025-01-16 Size : 1kb Publisher : Aaron
top_clock-plus Downloaded：0: After entering the basic clock signal, seconds, fractions, changes in the number of hours of simulation on a 24-hour clock quartus
Update : 2025-01-16 Size : 1.52mb Publisher : bajie
LCD1602 Downloaded：0: LCD1602 LCD with VHDL language to write the display string
Update : 2025-01-16 Size : 3.08mb Publisher : 赵嘉楠
half_integer Downloaded：0: half-integer frequency divider
Update : 2025-01-16 Size : 208kb Publisher : litong
ARINC_429 Downloaded：0: FPGA implementation ARINC429 protocol using verilog HDL to do a complete ARINC429 communication transceiver protocol, EDA development platform quartus ii9.1.
Update : 2025-01-16 Size : 4kb Publisher : 何俊
AMBA Downloaded：0: AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave
Update : 2025-01-16 Size : 17kb Publisher : zhch26
of Downloaded：0: VHDL source OFDM signal transmission system based on
Update : 2025-01-16 Size : 2.64mb Publisher : zhch21
SHIFT4_Parallel-input-serial-output Downloaded：0: Four serial input and parallel output shift register and shift register of the source code of pseudo-random sequence and correlation analysis
Update : 2025-01-16 Size : 773kb Publisher : FANFAN
compare2bits Downloaded：0: Sun yat-sen university digital design and computer architecture- 2 a design and implementation of the comparator
Update : 2025-01-16 Size : 80kb Publisher : FANFAN
MUX2_4bit Downloaded：0: Digital design and computer architecture- complete the four alternatives with verilog language data selector design
Update : 2025-01-16 Size : 67kb Publisher : FANFAN

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