VHDL-FPGA-Verilog List Page 328

VHDL-FPGA-Verilog list

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eetop.cn_Uvm_spi_bl_reg_tb Downloaded：0: uvm apb verification env
Update : 2025-01-16 Size : 225kb Publisher : 杨磊
fifo Downloaded：0: FIFO is determined by the clock is synchronous or asynchronous, synchronous FIFO read and write operations are a common clock control. on the other hand. Two different frequencies or different flavor to control the clock
Update : 2025-01-16 Size : 3kb Publisher : Isabelle Cheung
IIR Downloaded：0: IIR digital filter is a linear filter is the most common type. At a given time IIR input depending on their previous input and output values.
Update : 2025-01-16 Size : 47kb Publisher : Isabelle Cheung
ug480_7Series_XADC Downloaded：0: xinlinx V7 chip with verliog and vhdl realization comes adc analog acquisition
Update : 2025-01-16 Size : 20kb Publisher : wangsir
8b10b_endecode Downloaded：0: an 8b10b decoder, based on files Martin R and IBM paper
Update : 2025-01-16 Size : 9kb Publisher : adfadf
X4_8B10B Downloaded：0: 8b 4 times the conversion rate of turn 10b encoding and decoding procedures have been verified. ALTERA official code, encoding and decoding two files
Update : 2025-01-16 Size : 4kb Publisher : adfadf
crc Downloaded：0: CRC checksum of the source code for ethernet, ALTERA official code, verified
Update : 2025-01-16 Size : 3kb Publisher : adfadf
verilog_uart Downloaded：0: verilog prepared uart source code, altera official code, verified
Update : 2025-01-16 Size : 4kb Publisher : adfadf
double_addsub Downloaded：0: verilog source code and testbench double word addition and subtraction, and has been tested
Update : 2025-01-16 Size : 3kb Publisher : adfadf
pipeline_add Downloaded：0: pipeline type accumulator verilog testbench code and documents, verified
Update : 2025-01-16 Size : 4kb Publisher : adfadf
UD_DIVDER Downloaded：0: Customized divider verilog source code, variable frequency divider parameterized, easy to use
Update : 2025-01-16 Size : 3kb Publisher : adfadf
gray_counter Downloaded：0: altera official Gray code counter verilog code and testbench, have been tested
Update : 2025-01-16 Size : 5kb Publisher : adfadf

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