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VHDL-FPGA-Verilog list
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FIFO code in verilog
Update : 2024-12-25 Size : 1kb Publisher : shahzadsaahil

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The newest UVM IEEE standard(2017)
Update : 2024-12-25 Size : 2.72mb Publisher : timo_liu

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The design of FPGA, the reference clock frequency module, this module is provided in the peripheral circuit of the 50MHZ frequency, the clock module generates a clock signal after a second second, also provides the clock
Update : 2024-12-25 Size : 6.02mb Publisher : i belive

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(1) 24 hour time display (time, minute, second); (2) have time setting function (time and minute); (3) it has the function of whole point. (4) realize the alarm clock function (timing, noise);
Update : 2024-12-25 Size : 4.15mb Publisher : Goddd

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Simple combinatorial logic design, design of simple frequency division sequential logic circuit and Realization of counting frequency division timing circuit by conditional statement
Update : 2024-12-25 Size : 1kb Publisher : 随风sf

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Using a function in Verilog, a complex combinational logic circuit is realized with a always block, and the difference between blocking assignment and non blocking assignment
Update : 2024-12-25 Size : 1kb Publisher : 随风sf

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Using Verilog to write traffic light control code, can run the simulation directly.
Update : 2024-12-25 Size : 12kb Publisher : 王家小丫头

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DDS generate diagram program
Update : 2024-12-25 Size : 4.76mb Publisher : shilj

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The VERILOG code designed by UART, which has the function of FIFO, can realize the communication between the data and the instruction between the CPU and the peripherals
Update : 2024-12-25 Size : 535kb Publisher : 沐羽1996

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Hardware implementation of a piccolo cryptographic algorithm designed by Verilog
Update : 2024-12-25 Size : 4kb Publisher : longfor

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hwaccel = get_hwaccel
Update : 2024-12-25 Size : 16kb Publisher : 中国大

Shifter_Modified 4-bit SISO shift register.
Update : 2018-03-08 Size : 1.86kb Publisher : mamine2ia
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