VHDL-FPGA-Verilog List Page 81

VHDL-FPGA-Verilog list

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秒表 Downloaded：0: The stopwatch, VGA display, can modify the time, can set the alarm clock
Update : 2024-12-26 Size : 2.59mb Publisher : 小二郎儿
IC设计流程和设计方法 Downloaded：0: The design of IC can be divided into two parts: front-end design (also called logic design) and back-end design (also known as physical design). These two parts do not have a uniform and strict boundary, and the design r
Update : 2024-12-26 Size : 888kb Publisher : 叮咯咙咚呛36
Archive Downloaded：0: FPGA Basics FPGA coding
Update : 2024-12-26 Size : 2.63mb Publisher : ubaid
microblaze实例教程 Downloaded：0: Generally speaking, Xilinx Microblaze will be used to do some auxiliary work of control class and simple interface in the system, such as running low-speed interface driver such as IIC, SPI and UART, initializing configu
Update : 2024-12-26 Size : 25.68mb Publisher : 叮咯咙咚呛36
scia_loopback Downloaded：0: Ti C2000 F28069 USB to Mouse example
Update : 2024-12-26 Size : 6kb Publisher : JoeZhouq
Vivado使用教程 Downloaded：0: This is a tutorial on the use of VIVADO, for beginners, it is very useful
Update : 2024-12-26 Size : 2.47mb Publisher : 记忆中的我
KEY Downloaded：0: Using the key to control the LED lamp with Verilog is a good exercise for the beginner.
Update : 2024-12-26 Size : 1.23mb Publisher : 记忆中的我
ALU32 Downloaded：0: The 32 bit ALU is realized by using the Booth algorithm.
Update : 2024-12-26 Size : 1.68mb Publisher : jetyeah
北航MIPS多周期 Downloaded：0: The Verilog implementation of a multi cycle pipelined processor.
Update : 2024-12-26 Size : 13.9mb Publisher : jetyeah
他和它的故事 VerilogHDL之系列笔记 Downloaded：0: Some thoughts and notes on the Verilog experiment.
Update : 2024-12-26 Size : 23.21mb Publisher : jetyeah
Receiver_spartn6_v1 Downloaded：0: Implement design of UART receiver in verilog
Update : 2024-12-26 Size : 40kb Publisher : Armaghan
bcd counter Downloaded：0: Binary counter design in verilog
Update : 2024-12-26 Size : 172kb Publisher : Armaghan

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