VHDL-FPGA-Verilog List Page 79

VHDL-FPGA-Verilog list

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uart Downloaded：0: uart serial interface example
Update : 2024-12-25 Size : 10kb Publisher : davidren
random_check Downloaded：0: A message trap in a random stream, written by Verilog, is used to record the number of "1" in a message. When the packet capture device detects the sequence of "1101" appearing in the random code stream, it is recognized
Update : 2024-12-25 Size : 953kb Publisher : wanwan000
26518282FPGA Downloaded：0: The application of ep2c20f484n has a great effect
Update : 2024-12-25 Size : 9.03mb Publisher : (⊙﹏⊙)
CPU-Pipeline Downloaded：0: Five-stage pipeline CPU project files, including the serial port. vivado Verilog language. This CPU can do simple mathematical addition.
Update : 2024-12-25 Size : 14kb Publisher : Si Cheng
55680576lift Downloaded：0: The intelligent control of the elevator is a good choice of graduation design
Update : 2024-12-25 Size : 282kb Publisher : 二维星空
1 Downloaded：0: curcuit simulation in Hspice
Update : 2024-12-25 Size : 4kb Publisher : Shayesteh
数字钟 Downloaded：0: Digital clock
Update : 2024-12-25 Size : 15kb Publisher : 随风走
DDS的VERILOG原代码 Downloaded：0: ajhsjdhjkshfjhfsjkjksa
Update : 2024-12-25 Size : 3kb Publisher : 骑单车追飞机
20180125_5M_01 Downloaded：0: A pseudo-random binary sequence based on verilog.
Update : 2024-12-25 Size : 4.5mb Publisher : 沿途ing
LS165 Downloaded：0: The writing of the Verilog language of LS165 shift register
Update : 2024-12-25 Size : 361kb Publisher : sagee
count Downloaded：0: Writing a counter in the Verilog language
Update : 2024-12-25 Size : 381kb Publisher : sagee
LS164 Downloaded：0: Implementation of the LS164 shift register with Verilog
Update : 2024-12-25 Size : 354kb Publisher : sagee

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