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VHDL-FPGA-Verilog list
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FPGA8 shuma
Downloaded:0
Four digit tubes display eight digit numbers and roll playback
Update
: 2024-12-25
Size
: 763kb
Publisher
:
sagee
vc2015_x64_14.0.24215
Downloaded:0
Microsoft Visual C++ 2015 Redistributable(x64) - 14.0.24215
Update
: 2024-12-25
Size
: 12.93mb
Publisher
:
不名存在
_uart_test2
Downloaded:0
data transmitted from FPGA to PC using COM PORT version 2
Update
: 2024-12-25
Size
: 8kb
Publisher
:
anh92
_spi_test1
Downloaded:0
data transmitted from FPGA to devices using SPI bus
Update
: 2024-12-25
Size
: 7.69mb
Publisher
:
anh92
add.v
Downloaded:0
This is an adder by Verilog. It can be used for VLSI design.
Update
: 2024-12-25
Size
: 1kb
Publisher
:
limiduo
sdram_ov7670_vga
Downloaded:0
Image acquisition using FPGA
Update
: 2024-12-25
Size
: 5.18mb
Publisher
:
让我娘家看
图像中值滤波FPGA实现V1.0
Downloaded:1
The realization of the median filter function of the image, the file has the effect of display
Update
: 2024-12-25
Size
: 28.64mb
Publisher
:
gxgone
Verilog的边沿检测技术_设计源代码
Downloaded:0
The detection program of the rising descending edge of the waveform data has been verified by simulation
Update
: 2024-12-25
Size
: 36kb
Publisher
:
gxgone
dpll
Downloaded:0
The introduction of the digital full phase locked loop is introduced, and the realization principle and the implementation steps of the digital phase locked loop are described
Update
: 2024-12-25
Size
: 188kb
Publisher
:
CrazyICer
xapp1052
Downloaded:0
Xilinx PCIe official routines, the official website to download the required registration login, here give you another choice
Update
: 2024-12-25
Size
: 2.75mb
Publisher
:
gxgone
Vivado 2016.4 SRIO License
Downloaded:1
Vivado 2016.4 SRIO License, which has been passed in the Vivado 2016.4 test, can produce a bit stream. The other versions are not tested, and the estimates are also available.
Update
: 2024-12-25
Size
: 3.74mb
Publisher
:
飞翔的雄鹰
i2c_master_ip_for_nios
Downloaded:0
i2c master ip for altera nios, add in qsys
Update
: 2024-12-25
Size
: 213kb
Publisher
:
kevinfeng83
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