Description: verilog implementation stopwatch program. This procedure can be modified, but the show clock designs. Design can be according to the need to achieve every second. At the same time can change is the LED-running and other procedures. Very powerful!
To Search:
- [Verilog(clock)] - Verilog language using an electronic bel
- [clock] - Verilog HDL language-based electronic be
- [50M] - verilog language sub-frequency module, u
- [TurboCode11] - turbo code matlab simulation codes
- [LED] - To achieve digital control of the second
- [123] - Verilog是广泛应用的硬件描述语言，可以用在硬件设计流程的建模、综合和模拟等
- [6.1] - FPGA realization of multi-function alarm
File list (Check if you may need any files):
clock\p7seg.v
.....\bcdcnt.v
.....\clock.bdf
.....\clock.qpf
.....\clock.qsf
.....\bcdcnt.bsf
.....\clock.done
.....\p7seg.bsf
.....\fenpin.v
.....\fenpin.bsf
.....\clock.map.summary
.....\clock.flow.rpt
.....\clock.map.rpt
.....\clock.pin
.....\clock.fit.smsg
.....\clock.fit.summary
.....\clock.fit.rpt
.....\clock.asm.rpt
.....\fenpin4.v
.....\clock.sof
.....\clock.pof
.....\clock.tan.rpt
.....\fenpin.v.bak
.....\fenpin4.bsf
.....\clock.tan.summary
.....\fenpin4.v.bak
.....\bcdcnt.v.bak
.....\clock.vwf
.....\clock.dpf
.....\p7seg.v.bak
.....\clock.map.smsg
.....\clock.sim.rpt
.....\fenpin16.v
.....\fenpin16.bsf
.....\fenpin16.v.bak
.....\clock.qws
.....\clock.cdf
.....\db\wed.wsf
.....\..\clock.db_info
.....\..\clock.tan.qmsg
.....\..\clock.cmp.rdb
.....\..\clock.sld_design_entry.sci
.....\..\prev_cmp_clock.qmsg
.....\..\prev_cmp_clock.map.qmsg
.....\..\clock.map.qmsg
.....\..\clock.map_bb.logdb
.....\..\clock.eco.cdb
.....\..\prev_cmp_clock.asm.qmsg
.....\..\prev_cmp_clock.tan.qmsg
.....\..\clock.fit.qmsg
.....\..\clock.sgdiff.hdb
.....\..\prev_cmp_clock.fit.qmsg
.....\..\clock.asm.qmsg
.....\..\clock.rtlv.hdb
.....\..\clock.pre_map.cdb
.....\..\clock.signalprobe.cdb
.....\..\clock.map.cdb
.....\..\clock.cbx.xml
.....\..\clock.hif
.....\..\clock.sgdiff.cdb
.....\..\clock.cmp.logdb
.....\..\clock.sim.qmsg
.....\..\clock.rtlv_sg.cdb
.....\..\clock.rtlv_sg_swap.cdb
.....\..\clock.hier_info
.....\..\clock.pre_map.hdb
.....\..\clock.sld_design_entry_dsc.sci
.....\..\clock.map_bb.cdb
.....\..\clock.psp
.....\..\clock.dbp
.....\..\clock.pss
.....\..\clock.map.hdb
.....\..\clock.cmp.ecobp
.....\..\clock.map.bpm
.....\..\clock.cmp_bb.logdb
.....\..\clock.map_bb.hdb
.....\..\clock.syn_hier_info
.....\..\clock.map.logdb
.....\..\clock.cmp.tdb
.....\..\clock.cmp.cdb
.....\..\clock.sim.hdb
.....\..\clock.cmp.hdb
.....\..\clock.map.ecobp
.....\..\clock.cmp_bb.hdb
.....\..\clock.cmp_bb.cdb
.....\..\clock.cmp.bpm
.....\..\clock.eds_overflow
.....\..\clock.sim.cvwf
.....\..\clock.sim.rdb
.....\..\clock.tis_db_list.ddb
.....\..\clock.cmp0.ddb
.....\..\clock.cmp_bb.rcf
.....\db
clock
Download