Description: Use FPGA to implement DDS, given any frequency triangle wave, square wave or sine wave
- [DDS_Power] - FPGA on the verilog language programming
- [DDSFPGA_cylone] - dds design, spent a week doing, verilog
- [dds] - FPGA realization of DDS, f = 90kHZ ~ 5MH
- [FPGADDS] - dds, FPGA waveform generator, wave form,
- [DDS] - FPGA-based DDS program, can generate any
- [dds] - Using DDS technology, the use of FPGA ch
- [prog_dds] - FPGA VHDL DDS program, using FPGA to ach
- [sin5] - DDS FPGA 正弦波 VHDL语言
- [fpga] - Fpga write VHDL program can generate tri
- [equivalent_sample] - FPGA-based equivalent sampling system de
File list (Check if you may need any files):
FPGA(DDS)\DDS2\db\DDS2.asm.qmsg
.........\....\..\DDS2.cbx.xml
.........\....\..\DDS2.cmp.cdb
.........\....\..\DDS2.cmp.hdb
.........\....\..\DDS2.cmp.kpt
.........\....\..\DDS2.cmp.logdb
.........\....\..\DDS2.cmp.rdb
.........\....\..\DDS2.cmp.tdb
.........\....\..\DDS2.cmp0.ddb
.........\....\..\DDS2.dbp
.........\....\..\DDS2.db_info
.........\....\..\DDS2.eco.cdb
.........\....\..\DDS2.fit.qmsg
.........\....\..\DDS2.hier_info
.........\....\..\DDS2.hif
.........\....\..\DDS2.map.cdb
.........\....\..\DDS2.map.hdb
.........\....\..\DDS2.map.logdb
.........\....\..\DDS2.map.qmsg
.........\....\..\DDS2.pre_map.cdb
.........\....\..\DDS2.pre_map.hdb
.........\....\..\DDS2.psp
.........\....\..\DDS2.rtlv.hdb
.........\....\..\DDS2.rtlv_sg.cdb
.........\....\..\DDS2.rtlv_sg_swap.cdb
.........\....\..\DDS2.sgdiff.cdb
.........\....\..\DDS2.sgdiff.hdb
.........\....\..\DDS2.signalprobe.cdb
.........\....\..\DDS2.sld_design_entry.sci
.........\....\..\DDS2.sld_design_entry_dsc.sci
.........\....\..\DDS2.syn_hier_info
.........\....\..\DDS2.tan.qmsg
.........\....\DDS2.asm.rpt
.........\....\DDS2.bdf
.........\....\DDS2.bsf
.........\....\DDS2.done
.........\....\DDS2.fit.rpt
.........\....\DDS2.fit.summary
.........\....\DDS2.flow.rpt
.........\....\DDS2.map.rpt
.........\....\DDS2.map.summary
.........\....\DDS2.pin
.........\....\DDS2.qpf
.........\....\DDS2.qsf
.........\....\DDS2.qws
.........\....\DDS2.tan.rpt
.........\....\DDS2.tan.summary
.........\...L\db\altsyncram_ijk1.tdf
.........\....\..\DDSL.asm.qmsg
.........\....\..\DDSL.cbx.xml
.........\....\..\DDSL.cmp.cdb
.........\....\..\DDSL.cmp.hdb
.........\....\..\DDSL.cmp.kpt
.........\....\..\DDSL.cmp.logdb
.........\....\..\DDSL.cmp.rdb
.........\....\..\DDSL.cmp.tdb
.........\....\..\DDSL.cmp0.ddb
.........\....\..\DDSL.dbp
.........\....\..\DDSL.db_info
.........\....\..\DDSL.eco.cdb
.........\....\..\DDSL.fit.qmsg
.........\....\..\DDSL.hier_info
.........\....\..\DDSL.hif
.........\....\..\DDSL.map.cdb
.........\....\..\DDSL.map.hdb
.........\....\..\DDSL.map.logdb
.........\....\..\DDSL.map.qmsg
.........\....\..\DDSL.pre_map.cdb
.........\....\..\DDSL.pre_map.hdb
.........\....\..\DDSL.psp
.........\....\..\DDSL.rtlv.hdb
.........\....\..\DDSL.rtlv_sg.cdb
.........\....\..\DDSL.rtlv_sg_swap.cdb
.........\....\..\DDSL.sgdiff.cdb
.........\....\..\DDSL.sgdiff.hdb
.........\....\..\DDSL.signalprobe.cdb
.........\....\..\DDSL.sld_design_entry.sci
.........\....\..\DDSL.sld_design_entry_dsc.sci
.........\....\..\DDSL.syn_hier_info
.........\....\..\DDSL.tan.qmsg
.........\....\DDS.bsf
.........\....\DDS.vhd
.........\....\DDSL.asm.rpt
.........\....\DDSL.bdf
.........\....\DDSL.done
.........\....\DDSL.fit.rpt
.........\....\DDSL.fit.summary
.........\....\DDSL.flow.rpt
.........\....\DDSL.map.rpt
.........\....\DDSL.map.summary
.........\....\DDSL.pin
.........\....\DDSL.qpf
.........\....\DDSL.qsf
.........\....\DDSL.qws
.........\....\DDSL.tan.rpt
.........\....\DDSL.tan.summary
.........\....\LOCK.bsf
.........\....\LOCK.vhd
.........\....\lpm_ram_dp0.bsf
.........\....\lpm_ram_dp0.cmp
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