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[VHDL-FPGA-Verilogdds_quicklogic

Description: 这是quicklogic公司的直接频率合成(DDS)Verilog代码-QuickLogic Corporation This is a direct frequency synthesizer (DDS) Verilog code
Platform: | Size: 22528 | Author: jinzhoulang | Hits:

[VHDL-FPGA-VerilogAD9852

Description: 数字频率合成器芯片AD9852 的配置文件,HDL级的Verilog代码-DDS chip AD9852 profile, HDL-level Verilog code
Platform: | Size: 1024 | Author: 李春阳 | Hits:

[VHDL-FPGA-VerilogDDSverilogsource

Description: DDS的VERILOG原代码,请大家多支持-DDS of the Verilog source code, please support the U.S. more than
Platform: | Size: 3072 | Author: 屈开 | Hits:

[VHDL-FPGA-Verilogsine

Description: Verilog编程,利用FPGA实现两路正弦波的信号输出,也可以扩展成六路正弦输出-Verilog programming, the use of FPGA realize two sinusoidal output signals can also be extended into a six-way sinusoidal output
Platform: | Size: 4792320 | Author: 陈剑 | Hits:

[SCMdds_quicklogic

Description: dds直接频率合成源代码,基于rom表方式-dds a direct frequency synthesizer source code, based on the way rom Table
Platform: | Size: 22528 | Author: zhangxi | Hits:

[Other Embeded programdds_drive.c

Description: DDS发生器NIOS .c文件,在NIOSII中可以配合Verilog代码生成的自定义外设产生DDS信号-DDS generator NIOS. C files, NIOSII can be in Verilog code generation with custom peripherals DDS generated signal
Platform: | Size: 4096 | Author: 白天 | Hits:

[SCMDDS

Description: 直接频率合成仿真源程序,希望有人能用到.-Direct frequency synthesizer simulation source code, hope someone can use to.
Platform: | Size: 10240 | Author: bajunsheng | Hits:

[VHDL-FPGA-Verilogaccumulator

Description: 实现累加器的verilog源码,广泛应用在通信电路设计中-The realization of accumulator Verilog source, widely used in communication circuit design
Platform: | Size: 1024 | Author: 文明 | Hits:

[Other Embeded programDDS

Description: this a code for DDS in Verilog-this is a code for DDS in Verilog
Platform: | Size: 2048 | Author: SID17 | Hits:

[VHDL-FPGA-VerilogcordicDDS

Description: Cordic算法实现DDS的Verilog 源码,14位精度,非常实用的。-DDS algorithm Cordic the Verilog source code, 14-bit accuracy, very practical.
Platform: | Size: 7168 | Author: 王王 | Hits:

[VHDL-FPGA-VerilogFPGA-DDS

Description: 在FPGA内,以查表方式实现频率直接合成器(DDS)功能。verilog源代码-In the FPGA in order to achieve the look-up table means the direct synthesizer frequency (DDS) feature. verilog source code
Platform: | Size: 2048 | Author: niuqs | Hits:

[VHDL-FPGA-VerilogDDSVerilog

Description: DDS Verilog 代码。包含英文文档说明-DDS Verilog code. Containing the English documentation
Platform: | Size: 71680 | Author: caixiang | Hits:

[VHDL-FPGA-VerilogDDS

Description: DDS数字频率合成的verilog代码,附有正余弦查找表等-DDS digital frequency synthesis verilog code, with a cosine look-up table, etc.
Platform: | Size: 16772096 | Author: allen-haha | Hits:

[VHDL-FPGA-Verilogddsfinal1

Description: verilog语言实现的dds代码,并行通信,生成四种波形,大赛编写的代码,modelsim仿真-verilog language dds code,modelsim debug
Platform: | Size: 1137664 | Author: 杨天 | Hits:

[VHDL-FPGA-VerilogDDS

Description: 关于用FPGA制作的DDS源代码。用的是verilog语言,用的是xlinx的软件-Produced with the DDS on FPGA source code. Using verilog language, using xlinx software
Platform: | Size: 5120 | Author: 张君 | Hits:

[VHDL-FPGA-VerilogDDS-in-Verilog

Description: Verilog编写基于FPGA的DDS实现,内含源代码,希望对大家有所帮助。-DDS in Verilog FPGA-based implementation, including source code, we want to help.
Platform: | Size: 464896 | Author: haby | Hits:

[VHDL-FPGA-VerilogDDS-VERILOG

Description: DDS的信号发生器verilog代码 可直接用于编程 已经测试-Verilog code of the DDS signal generator which can be used directly in the programming has been tested
Platform: | Size: 3072 | Author: 佘琪 | Hits:

[Software EngineeringDDS-Verilog

Description: DDS设计的源代码 用于生成高精度的DDS程序 VERILOG-VERILOG DDS DDS program design source code used to generate high-precision
Platform: | Size: 8192 | Author: hdl | Hits:

[Documentscordic

Description: 基于cordic算法的DDS的Verilog代码。经过仿真验证,绝对可靠。-Based on cordic algorithm DDS Verilog code. Through the simulation, is absolutely reliable.
Platform: | Size: 1985536 | Author: longgege | Hits:

[VHDL-FPGA-Verilogdds

Description: 采用硬件描述语言verilog进行DDS变换的实现的代码-Using hardware description languages Verilog implementation of DDS converter code
Platform: | Size: 1024 | Author: 何晨光 | Hits:
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